Abstract: A chip includes a merger cell including a first p-type length of diffusion (LOD) region extending in a first direction, a first n-well underneath the first p-type LOD region, a first supply rail configured to receive a first supply voltage, and a first n-tap coupling the first n-well to the first supply rail. The merger cell also includes a second p-type length of diffusion (LOD) region extending in the first direction, a second n-well underneath the second p-type LOD region, a second supply rail configured to receive a second supply voltage different from the first supply voltage, and a second n-tap coupling the second n-well to the second supply rail.

Abstract: Methods, apparatus, systems and articles of manufacture to compensate radar system calibration are disclosed. A radio-frequency (RF) subsystem having a transmit channel, a receive channel, and a loopback path comprising at least a portion of the transmit channel and at least a portion of the receive channel, a loopback measurer to measure a first loopback response of the RF subsystem for a first calibration configuration of the RF subsystem, and to measure a second loopback response of the RF subsystem for a second calibration configuration of the RF subsystem, and a compensator to adjust at least one of a transmit programmable shifter or a digital front end based on a difference between the first loopback response and the second loopback response to compensate for a loopback response change when the RF subsystem is changed from the first calibration configuration to the second calibration configuration.

Abstract: A method for quadrature phase shifted clock generation with duty cycle correction includes A reference clock is delayed with a delay circuit to generate a delayed clock, wherein a delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock comprise a plurality of states comprising a first state and a second state. A first edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. A second edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. The control value is driven to the first edge value during the second state of the delayed clock and to the second edge value during the first state of the delayed clock.

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

Abstract: A network-communicating device with a signal input adapted to receive a sensor-derived signal; an analog-to-digital converter (ADC) having an input coupled to the signal input and an output; a data scrambling circuit having an input coupled to the output of the ADC and an output; a watermark insertion circuit having an input coupled to the output of the data scrambling circuit and an output; and a signal output coupled to the output of the watermark insertion circuit.

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

Abstract: The disclosed technology relates to improved user authentication to verify transaction legitimacy. An exemplary system may send a request for a current image to a mobile device associated with a user. The request may include an indication of a requested action to be performed by the user. The system may classify an action depicted in the current image obtained in response to the request. A determination may be made as to whether the depicted action corresponds to the requested action based on the classification. When it does correspond, the system may compare facial feature(s) recognized in obtained past image(s) associated with the user to a facial feature(s) recognized in the current image to determine when the user is depicted in both the past image(s) and the current image. When the user is depicted in both the past image(s) and the current image, the system may allow the transaction to proceed.

Abstract: Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

Abstract: A device includes first and second circuits. The first circuit includes a temperature sensor to measure a device temperature. The second circuit operates to send an enable signal to the first circuit to cause the temperature sensor to measure the device temperature; and, in response to not receiving at least one of a ready signal and the device temperature from the first circuit within a set amount of time, output a tamper event signal and a timeout event signal, and disable a valid data signal.

Abstract: Embodiments of symmetric flow valves for use in substrate processing chambers are provided herein. In some embodiments, a symmetric flow valve includes: a valve body having sidewalls, a bottom plate, and a top plate that together define an interior volume, wherein the top plate includes a plurality of axisymmetrically disposed openings arranged in a non-linear manner, and wherein the bottom plate includes a port opening; an actuator disposed above the top plate and coupled to a central region of the top plate radially inward of the plurality of axisymmetrically disposed openings; and a poppet disposed in the interior volume and coupled to the actuator to move the poppet vertically within the interior volume, wherein the poppet is configured to selectively seal the plurality of axisymmetrically disposed openings or the port opening.

Abstract: A method for imaging a subject using a magnetic resonance imaging (MRI) system includes determining a tailored radio frequency (RF) pulse sequence having a plurality of refocusing pulses. In the method, a target peak RF pulse value is determined and a transfer function to convert a first refocusing pulse of the plurality of refocusing pulses to a modified refocusing pulse with the target peak RF pulse value is also determined. A modified RF pulse sequence is generated based on the transfer function and the plurality of refocusing pulses. Finally, magnetic resonance (MR) signals from the subject are acquired based on the modified RF pulse sequence and the medical image of the subject is generated based on the acquired MR signals.

Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.

Abstract: Smart labels, methods of operating smart labels, and associated contexts in which such smart labels may be used are disclosed. The smart label, for use in conjunction with consumer product packaging, comprises an energy harvester to capture ambient energy to provide a source of electrical energy and electronic circuitry powered by the electrical energy. A fuse provides an electrical connection between the energy harvester and the electronic circuitry and destruction of the fuse permanently disconnects the energy harvester from the electronic circuitry. Unnecessary continued operation of the electronic circuitry powered by the energy harvester can therefore be prevented, for example when the consumer product packaging is disposed of or recycled, which may be an undesirable heat source. Smart labelling, and a connected network of smart bins which can read the smart labelling, may also be used to promote consumer recycling of consumer product packaging.

Abstract: The present invention relates to a method (300) for drawing an optical fiber (101) having step of stacking (302) at least two glass sub-preforms of a plurality of glass sub-preforms (114a-114n) inside a hollow cylindrical glass tube (108) to form a master glass preform (130) and melting (304) the bottom end (134) of the master glass preform (130) in a furnace (110) to continuously draw an optical fiber (101). In particular, the at least two glass sub-preforms are stacked in such that the master glass preform has a top end (132) and a bottom end (134) and each of the glass sub-preforms is defined by a first end (126) and a second end (128). Further, the first end (126) of a successive glass sub-preform is stacked on the second end (128) of a previous glass sub-perform such that the successive glass sub-preform rests on the previous glass sub-preform.

Abstract: A network-communicating device with an analog-to-digital converter (ADC) having an output and encryption and selectivity circuitry for encrypting selected output values from the ADC.

Abstract: A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC.

Abstract: This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

Abstract: In an example, a device includes a controller and a direct current (DC)-to-DC converter coupled to the controller and configured to provide a load current to a load. The device also includes a low-dropout (LDO) regulator coupled to the DC-to-DC converter. The controller includes digital logic, and the digital logic is configured to determine the load current. The digital logic is configured to turn on the LDO regulator if the load current is above a predetermined threshold. The digital logic is also configured to turn off the LDO regulator if the load current is below the predetermined threshold.

Abstract: Described herein are novel stable 9-N-, 8-N-, and 7-N-acetyl analogues of instable 9-O-acetyl, 8-O-acetyl, and 7-O-acetyl b-series gangliosides and glycosphingosines, including GD3, GD2, GD1b, GT1b, GQ1b, and their glycosphingosines. Chemoenzymatic methods for the production of the stable 9-N-, 8-N-, and 7-N-acetyl analogues are also described herein.

Abstract: A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.