Abstract: An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.

Abstract: A compensation system for a crystal oscillator including a DC level comparator, current compensation circuitry, and a compensation controller. The crystal oscillator includes an amplifier with a feedback resistance coupled between first and second terminals of a crystal resonator. The DC level comparator may be a hysteretic comparator that compares a DC level of the first node with a DC level of the second node and to provide a corresponding compensation signal. The compensation controller controls a magnitude and direction of the compensation current applied to the first node by the current compensation circuitry based on the compensation signal. The current compensation circuitry sources current to or sinks current from the first node until the leakage current is minimized. The compensation controller may include a digital counter the generates a digital control value used to activate selected current sources or sinks for developing the compensation current.

Abstract: A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

Abstract: A device may cause a Media Access Control Security (MACsec) session to be established on a first link of a link aggregation group (LAG) that includes a plurality of links with a different device. The device may cause a data structure to be updated to identify the first link as a MACsec enabled LAG link and may send traffic via the first link. The device may cause a MACsec session to be established on at least one additional link of the LAG and may cause the data structure to be updated to identify the at least one additional link as a MACsec enabled LAG link. The device may send, after causing the data structure to be updated to identify the at least one additional link as a MACsec enabled LAG link, additional traffic via the first link and the at least one additional link.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to protect against voltage glitch attacks in microcontrollers. An example apparatus includes logic circuitry operable to, in response to a voltage glitch, pause processing circuitry; number generator circuitry operable to generate a number; a counter operable to, after the voltage glitch ends, adjust a count corresponding to the number; and the logic circuitry operable to unpause the processing circuitry after the count reaches a value.

Abstract: Example aspects include techniques for providing an auditable mechanism for internal services to transact on tenant entities. These techniques may include receiving, from an internal service, by an assistant service, a service request to perform a cloud computing action over tenant data of a tenant of a cloud computing environment. In addition, the techniques may include identifying, by the assistant service, an existing principal of the assistant service within the tenant and possession of an existing permission associated with performing the cloud computing action within the tenant of the cloud computing environment. Further, the techniques may include performing the cloud computing action on behalf of the internal service based on identifying the existing principal and possession of the existing permission.

Abstract: A method, apparatus, non-transitory computer readable medium, and system for generating a design document from a text prompt include obtaining a design prompt that describes a document type and selecting a design template for the document type based on the design prompt. An image generation model generates an image for the design template based on the design prompt and a design document is generated based on the design template. The design document has the document type and includes the image at a location indicated by the design template.

Abstract: A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.

Abstract: A system disclosed herein may receive, from an application associated with a client identification, a request to perform a cryptographic operation with a specified application key, identify a gateway associated with the client identification, identify a respective characteristic of each self-encrypting key management service of a plurality of self-encrypting key management services that correspond to the gateway, identify a self-encrypting key management service with a characteristic satisfying a threshold criterion, and send the request to the identified self-encrypting key management service.

Abstract: Vehicle systems and methods are provided for visually alerting a vehicle operator to a potential obstacle in the vicinity of a vehicle using an external lighting system associated with the vehicle. An exemplary method involves identifying an analysis portion of image data captured for a region external to the vehicle based at least in part on current status information associated with the vehicle, identifying an obstacle within the analysis portion of the image data based at least in part on ranging data for the analysis portion, and in response to identifying the obstacle, automatically adjusting an illumination axis associated with a lighting system to illuminate the obstacle, determining a current value for a contrast ratio associated with the obstacle relative to the analysis portion of the image data, and automatically adjusting one or more characteristics of the lighting system based at least in part on the current value.

Abstract: An apparatus may comprise a memory communicatively coupled to a processor. The processor may be configured to receive a request to perform multiple data processing operations and determine multiple sub-dialogues corresponding to the request. The sub-dialogues are part of a plurality of IVR operations. The processor may be further configured to route the request to a microservice of the microservices based at least in part upon the sub-dialogues. The microservice may be configured to fulfill the request. The processor may generate a response to the request associated with the microservice, update publishing commands in accordance with one or more rules and policies in response to generating the response, and publish the first microservice. The publishing commands associated with the microservice may be updated in isolation from the rest of the microservices.

Abstract: Systems and methods for controlled application of hysteresis in crystal oscillator circuits are discussed. In various embodiments, an Integrated Circuit (IC) may include: an inverter comparator coupled to a crystal oscillator, where the inverter comparator is configured to: (i) receive an input of the crystal oscillator, and (ii) output a clock signal; and a hysteresis control circuit coupled to the inverter comparator, wherein the inverter comparator is configured to: (i) start up with hysteresis disabled, and (ii) enable hysteresis in response to a hysteresis enable signal provided by the hysteresis control circuit.

Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.

Abstract: Example aspects include techniques for providing a compliant and auditable approach for a user to perform an action without sufficient privileges. These techniques may include receiving, from a first user account, a first request to perform an action and determining that the first user account does not have permission to perform the action. In addition, the techniques may include identifying a second user account having permission to perform the action and transmitting, to the second user account, a second request for approval to perform the action. Further, the techniques may include performing in response to approval of the second request, the action without providing the permission to the first user account.

Abstract: Systems and methods are provided for dynamic selection of anomaly detection options for particular metric data. Metric data corresponding to one or more configuration items of an information technology (IT) infrastructure is collected. A selected anomaly detection action option that applies to the metric data is identified. An action is performed using the metric data, based upon the selected anomaly detection action option. A dashboard graphical user interface (GUI) display results of the action.

Abstract: In an example, a device includes a controller and a direct current (DC)-to-DC converter coupled to the controller and configured to provide a load current to a load. The device also includes a low-dropout (LDO) regulator coupled to the DC-to-DC converter. The controller includes digital logic, and the digital logic is configured to determine the load current. The digital logic is configured to turn on the LDO regulator if the load current is above a predetermined threshold. The digital logic is also configured to turn off the LDO regulator if the load current is below the predetermined threshold.

Abstract: A video headset comprises a left earphone assembly, a right earphone assembly, and a headband assembly having a headband frame. The headband frame comprises a left end portion movably coupled to the left earphone assembly and a right end portion movably coupled to the right earphone assembly. The headset comprises a video screen module connected to each earphone assembly via a boom module. The video screen module comprises video screens including a first video screen and a second video screen pivotally connected to a second video screen. The second video screen faces in an opposite direction from the first video screen. The headset enables to stream both audio and video data at the video screen module. The headset is further configured to connect with external devices and stream data from different external devices on different video screens. The headset has multiple cameras on the headset to enable 360 degree viewing.

Abstract: Disclosed are systems and techniques for wireless communications. For example, a network device can divide a data package into a plurality of segments. The network device can transmit, to a plurality of wireless communication devices, a broadcast message indicating a first time to start receiving a plurality of subframes comprising the plurality of segments, a total number of the plurality of segments, and a total number of the plurality of subframes for the data package. The network device can transmit, to the plurality of wireless communication devices starting at the first time, the plurality of subframes comprising the plurality of segments.

Abstract: A system is presented that includes two data processing systems that are coupled via a network, each data processing system including a reconfigurable processor with a reconfigurable processor memory, a host that is coupled to the reconfigurable processor and that includes a host processor and a host memory that is coupled to the host processor, and a network interface controller (NIC) that is operatively coupled to the reconfigurable processor and to the host processor. The reconfigurable processor of one of the data processing systems is configured to implement a virtual function that uses a virtual address for a memory access operation. An application programming interface (API) in the host processor translates the virtual address into a physical address, and the NIC uses the physical address to initiate a direct memory access operation at the reconfigurable processor memory or the host memory of the other data processing system.