Patents by Inventor Anand Kumar

Anand Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12633939
    Abstract: Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses that may calibrate a resistor-capacitor (RC) circuit.
    Type: Grant
    Filed: February 29, 2024
    Date of Patent: May 19, 2026
    Assignee: STMicroelectronics International N.V.
    Inventors: Abhishek Jain, Anand Kumar
  • Patent number: 12614701
    Abstract: A plasma confinement screen system for a process chamber includes an inner plasma screen having an inner annular body with a central opening, the annular body including a plurality of first openings; and an outer plasma screen having an outer annular body with a central opening surrounding the inner plasma screen, the outer annular body including a plurality of second openings, wherein the outer plasma screen is configured for vertical movement relative to the inner plasma screen.
    Type: Grant
    Filed: May 15, 2024
    Date of Patent: April 28, 2026
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yogananda Vishwanath Sarode, Anand Kumar
  • Patent number: 12560243
    Abstract: Embodiments of symmetric flow valves for use in substrate processing chambers are provided herein. In some embodiments, a symmetric flow valve includes: a valve body having sidewalls, a bottom plate, and a top plate that together define an interior volume, wherein the top plate includes a plurality of axisymmetrically disposed openings arranged in a non-linear manner, and wherein the bottom plate includes a port opening; an actuator disposed above the top plate and coupled to a central region of the top plate radially inward of the plurality of axisymmetrically disposed openings; and a poppet disposed in the interior volume and coupled to the actuator to move the poppet vertically within the interior volume, wherein the poppet is configured to selectively seal the plurality of axisymmetrically disposed openings or the port opening.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: February 24, 2026
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chetan Ramachandra Naik, Anand Kumar
  • Publication number: 20250379090
    Abstract: A device includes a puck corresponding to an electrostatic chuck. The puck includes a backing region, a chucking region disposed on the backing region and having a plateau, and a set of electrodes embedded within the hybrid puck. The backing region includes a first dielectric material to improve thermal performance of the hybrid puck. The chucking region includes a second dielectric material different from the first dielectric material to improve leakage current stability. The set of electrodes includes a chucking electrode embedded within the chucking region.
    Type: Application
    Filed: August 25, 2025
    Publication date: December 11, 2025
    Inventors: Yogananda Sarode, Anand Kumar, Prashant V. Javali
  • Publication number: 20250357089
    Abstract: A plasma confinement screen system for a process chamber includes an inner plasma screen having an inner annular body with a central opening, the annular body including a plurality of first openings; and an outer plasma screen having an outer annular body with a central opening surrounding the inner plasma screen, the outer annular body including a plurality of second openings, wherein the outer plasma screen is configured for vertical movement relative to the inner plasma screen.
    Type: Application
    Filed: May 15, 2024
    Publication date: November 20, 2025
    Inventors: Yogananda Vishwanath SARODE, Anand KUMAR
  • Patent number: 12459071
    Abstract: In one example, a substrate support assembly having a cooling base that promotes temperature uniformity. In one embodiment, the cooling base has a top plate. The top plate has cooling channels formed therein. The cooling base has a middle plate. The middle plate has a cooling return plenum disposed on a middle layer. A plurality of islands are disposed in the cooling return plenum. The middle plate has a cooling supply plenum disposed below the middle layer. A plurality of cooling inlets are disposed through the islands and couple the cooling supply plenum to the cooling channels. Cooling outlets fluidly couple the cooling channels to the cooling return plenum. The cooling base has a bottom plate. The bottom plate has a cooling inlets fluidly coupled to cooling supply plenum and cooling outlets fluidly coupled to the cooling return plenum.
    Type: Grant
    Filed: January 10, 2024
    Date of Patent: November 4, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Yogananda Sarode Vishwanath, Anand Kumar
  • Patent number: 12444644
    Abstract: Apparatuses for substrate transfer are provided. A lift pin assembly can include a lift pin, a purge cylinder, and a lift pin guide. The lift pin guide is disposed adjacent the purge cylinder. The lift pin guide and the purge cylinder have a passage formed therethrough in which the lift pin is disposed. The purge cylinder includes one or more nozzles that direct the flow of gas radially inward into a portion of the passage disposed in the purge cylinder. The one or more nozzles are disposed radially outward from the lift pin. The purge cylinder reduces particle deposition on the substrate by preventing contact between the lift pin and the support assembly as the lift pin is in motion.
    Type: Grant
    Filed: April 19, 2024
    Date of Patent: October 14, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Yogananda Sarode Vishwanath, Anand Kumar
  • Publication number: 20250306314
    Abstract: Systems and methods are provided for maintaining Signal Integrity (SI) in an optical communications system while operating at high data rates. In an embodiment, a host device includes a Printed Circuit Board (PCB) including a first side with multiple rows of Ball Grid Array (BGA) contacts; and a first socket interface including a receptacle configured to receive a pluggable optical module for communication therewith, the socket interface further including multiple electrical conductors configured for electrical connection with the BGA contacts. Each row of the BGA contacts on the first side can include multiple first sets of contacts offset from each other in a first direction with respect to a planar surface of the first side of the PCB, such offset being advantageous in a belly-to-belly configuration.
    Type: Application
    Filed: May 9, 2024
    Publication date: October 2, 2025
    Applicant: Ciena Corporation
    Inventors: Rampratap Mahawar, Jai Mal Vardan, Sardeep Heda, Anand Kumar
  • Publication number: 20250299929
    Abstract: The present disclosure relates to a protective ring for an edge electrode, an edge voltage delivery system, and a substrate support assembly. The protective ring for a substrate support assembly includes an annular body including a first top surface and a first bottom surface; a protrusion disposed along an inner perimeter of the annular body and including a second top surface and a second bottom surface, the second top surface being disposed below the first top surface; and a skirt disposed along an outer perimeter of the annular body and extending downwardly from the first bottom surface. The skirt, the protrusion, and the first bottom surface form a groove under the annular body. The groove is configured to receive the edge electrode. Both the edge voltage delivery system and the substrate support assembly include the protective ring and the edge electrode.
    Type: Application
    Filed: March 25, 2024
    Publication date: September 25, 2025
    Inventors: Yogananda SARODE VISHWANATH, Rajinder DHINDSA, Anand KUMAR, Denis Martin KOOSAU, John POULOSE, James ROGERS
  • Patent number: 12412769
    Abstract: A device includes a hybrid puck corresponding to an electrostatic chuck. The hybrid puck includes a backing region and a chucking region disposed on the backing region. The backing region includes a first dielectric material to improve thermal performance of the hybrid puck. The chucking region includes a second dielectric material different from the first dielectric material to improve leakage current stability.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: September 9, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Yogananda Sarode, Anand Kumar, Prashant V. Javali
  • Publication number: 20250279313
    Abstract: A lid for a process chamber includes a first ceramic disc including a first dielectric material having a first thermal conductivity, a second ceramic disc including a second dielectric material having a second thermal conductivity, and a bond layer that bonds the second ceramic disc to the first ceramic disc. The first thermal conductivity may be greater than the second thermal conductivity.
    Type: Application
    Filed: March 4, 2024
    Publication date: September 4, 2025
    Inventors: Yogananda Sarode Vishwanath, Anand Kumar, Santosh Nesarkar, Imad Yousif, Harinath Reghunathanna, John Anthony O’Malley, III
  • Publication number: 20250222550
    Abstract: In one example, a substrate support assembly having a cooling base that promotes temperature uniformity. In one embodiment, the cooling base has a top plate. The top plate has cooling channels formed therein. The cooling base has a middle plate. The middle plate has a cooling return plenum disposed on a middle layer. A plurality of islands are disposed in the cooling return plenum. The middle plate has a cooling supply plenum disposed below the middle layer. A plurality of cooling inlets are disposed through the islands and couple the cooling supply plenum to the cooling channels. Cooling outlets fluidly couple the cooling channels to the cooling return plenum. The cooling base has a bottom plate. The bottom plate has a cooling inlets fluidly coupled to cooling supply plenum and cooling outlets fluidly coupled to the cooling return plenum.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 10, 2025
    Inventors: Yogananda SARODE VISHWANATH, Anand KUMAR
  • Patent number: 12314975
    Abstract: The disclosed embodiments provide systems, methods, and techniques for managing merchandising cards. A merchandising card may be, for example, a gift card, loyalty card, or the like. Consistent disclosed embodiments, a system for managing merchandising cards may include one or more memory devices storing instructions and one or more processors configured to acquire, from a device over a network, a plurality of locations associated with the device, the device locations being acquired at different instances in time within a predetermined period of time. Additionally, the one or more processors may be configured to calculate an overall merchant confidence rating for a merchant using the device locations. Further, the one or more processors may be configured to, based on the overall merchant confidence rating, determine that the merchant matches a merchant that is associated with merchandising card, and send a reminder a user of the device.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: May 27, 2025
    Assignee: Capital One Services, LLC
    Inventors: Dan Givol, Saumya Singh, Anand Kumar, Michelle S. Olenoski
  • Patent number: 12294372
    Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: May 6, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Jain, Anand Kumar, Kallol Chatterjee
  • Patent number: 12294348
    Abstract: A single stage electromagnetic interference (EMI) filter circuit includes a power source input configured to connect to a power source; an equivalent common mode and differential mode filter including a single inductor having both common mode inductance for common mode filtering and specific parasitic inductance; and a differential capacitance stage connected to the single inductor in parallel, wherein a combination of the specific parasitic inductance and capacitance of the differential capacitance stage are used to provide differential mode filtering.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: May 6, 2025
    Assignee: Ciena Corporation
    Inventors: Karan Goel, Chander Gupta, Sujoy Mandal, Anand Kumar
  • Patent number: 12273117
    Abstract: A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: April 8, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Prashutosh Gupta
  • Patent number: 12224710
    Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: February 11, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Nitin Jain
  • Publication number: 20250047279
    Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 6, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Vaibhav GARG, Abhishek JAIN, Anand KUMAR
  • Patent number: 12217259
    Abstract: The disclosed technology relates to improved user authentication to verify transaction legitimacy. An exemplary system may send a request for a current image to a mobile device associated with a user. The request may include an indication of a requested action to be performed by the user. The system may classify an action depicted in the current image obtained in response to the request. A determination may be made as to whether the depicted action corresponds to the requested action based on the classification. When it does correspond, the system may compare facial feature(s) recognized in obtained past image(s) associated with the user to a facial feature(s) recognized in the current image to determine when the user is depicted in both the past image(s) and the current image. When the user is depicted in both the past image(s) and the current image, the system may allow the transaction to proceed.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 4, 2025
    Assignee: CAPITAL ONE SERVICES, LLC
    Inventors: Kaush Kumar, Jennifer Chu, Anand Kumar
  • Publication number: 20250035215
    Abstract: Embodiments of symmetric flow valves for use in substrate processing chambers are provided herein. In some embodiments, a symmetric flow valve includes: a valve body having sidewalls, a bottom plate, and a top plate that together define an interior volume, wherein the top plate includes a plurality of axisymmetrically disposed openings arranged in a non-linear manner, and wherein the bottom plate includes a port opening; an actuator disposed above the top plate and coupled to a central region of the top plate radially inward of the plurality of axisymmetrically disposed openings; and a poppet disposed in the interior volume and coupled to the actuator to move the poppet vertically within the interior volume, wherein the poppet is configured to selectively seal the plurality of axisymmetrically disposed openings or the port opening.
    Type: Application
    Filed: July 24, 2023
    Publication date: January 30, 2025
    Inventors: Chetan Ramachandra NAIK, Anand KUMAR