Abstract: Smart labels, methods of operating smart labels, and associated contexts in which such smart labels may be used are disclosed. The smart label, for use in conjunction with consumer product packaging, comprises an energy harvester to capture ambient energy to provide a source of electrical energy and electronic circuitry powered by the electrical energy. A fuse provides an electrical connection between the energy harvester and the electronic circuitry and destruction of the fuse permanently disconnects the energy harvester from the electronic circuitry. Unnecessary continued operation of the electronic circuitry powered by the energy harvester can therefore be prevented, for example when the consumer product packaging is disposed of or recycled, which may be an undesirable heat source. Smart labelling, and a connected network of smart bins which can read the smart labelling, may also be used to promote consumer recycling of consumer product packaging.

Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.

Abstract: A network-communicating device with an analog-to-digital converter (ADC) having an output and encryption and selectivity circuitry for encrypting selected output values from the ADC.

Abstract: The present invention relates to an optical fiber 100 having a core (102) which is up doped and a cladding (104) surrounding the core (102). Particularly, the cladding (104) has a first cladding (104a) defined by a first relative refractive index difference (?1). Moreover, the first cladding (104a) is a continuous region adjacent to the core (102) such that a relative refractive index profile of the first cladding (104a) is an alpha profile. Further, the optical fiber (100) has mode field diameter in the range of 8.2 micrometer (?m) to 9.0 ?m at a wavelength of 1310 nanometer (nm), and a cut-off wavelength less than or equal to 1260 nm.

Abstract: An example method of managing a custom resource in a container orchestration (CO) system includes: receiving, from a manager at a management cluster of the CO system, an intent identifier, the management cluster including a controller configured to manage the custom resource, the management cluster storing the intent identifier in a database; receiving, from the manager at the management cluster, a request that updates state of the custom resource; determining, at the management cluster, a match between an intent identifier in the request and the intent identifier stored in the database; and executing, by the controller of the management cluster, a management process for the custom resource in the CO system in response to the match and the request.

Abstract: The present invention relates to a method (300) for drawing an optical fiber (101) having step of stacking (302) at least two glass sub-preforms of a plurality of glass sub-preforms (114a-114n) inside a hollow cylindrical glass tube (108) to form a master glass preform (130) and melting (304) the bottom end (134) of the master glass preform (130) in a furnace (110) to continuously draw an optical fiber (101). In particular, the at least two glass sub-preforms are stacked in such that the master glass preform has a top end (132) and a bottom end (134) and each of the glass sub-preforms is defined by a first end (126) and a second end (128). Further, the first end (126) of a successive glass sub-preform is stacked on the second end (128) of a previous glass sub-perform such that the successive glass sub-preform rests on the previous glass sub-preform.

Abstract: This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

Abstract: A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC.

Abstract: In an example, a device includes a controller and a direct current (DC)-to-DC converter coupled to the controller and configured to provide a load current to a load. The device also includes a low-dropout (LDO) regulator coupled to the DC-to-DC converter. The controller includes digital logic, and the digital logic is configured to determine the load current. The digital logic is configured to turn on the LDO regulator if the load current is above a predetermined threshold. The digital logic is also configured to turn off the LDO regulator if the load current is below the predetermined threshold.

Abstract: In various example embodiments, a system and method for consistent schema-less and scalable database storage are described herein. A data object is generated. The data object corresponds to a column of a table from a database. The data object includes information regarding an order that is placed over a network publication system. The data object is stored in the column of the table in the database. A request to access the data object is received from a device of a first user. The data object is transmitted to the device of the first user. The data is kept coherent during concurrent updates by using optimistic locks. The data is kept backward and forward compatible utilizing intermediate data structures common to both versions of the software. The data is kept searchable by using lookup indexes. The storage system is kept scalable by sharing data across many databases.

Abstract: A request to execute an application at a secure cryptographic environment of a server may be received. A tag that has been assigned to the application may be received. An attribute of the server may be identified. A determination may be made as to whether the attribute of the server satisfies the tag that has been assigned to the application. In response to determining that the attribute of the server satisfies the tag that has been assigned to the application, an indication may be provided to execute the application at the secure cryptographic environment of the server.

Abstract: Described herein are novel stable 9-N-, 8-N-, and 7-N-acetyl analogues of instable 9-O-acetyl, 8-O-acetyl, and 7-O-acetyl b-series gangliosides and glycosphingosines, including GD3, GD2, GD1b, GT1b, GQ1b, and their glycosphingosines. Chemoenzymatic methods for the production of the stable 9-N-, 8-N-, and 7-N-acetyl analogues are also described herein.

Abstract: A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.

Abstract: Systems and methods for controlled application of hysteresis in crystal oscillator circuits are discussed. In various embodiments, an Integrated Circuit (IC) may include: an inverter comparator coupled to a crystal oscillator, where the inverter comparator is configured to: (i) receive an input of the crystal oscillator, and (ii) output a clock signal; and a hysteresis control circuit coupled to the inverter comparator, wherein the inverter comparator is configured to: (i) start up with hysteresis disabled, and (ii) enable hysteresis in response to a hysteresis enable signal provided by the hysteresis control circuit.

Abstract: A device includes a hybrid puck corresponding to an electrostatic chuck. The hybrid puck includes a backing region and a chucking region disposed on the backing region. The backing region includes a first dielectric material to improve thermal performance of the hybrid puck. The chucking region includes a second dielectric material different from the first dielectric material to improve leakage current stability.

Abstract: An integrated circuit (IC), comprising a fuse structure (eFuse) formed in a resistive layer over a semiconductor substrate, the eFuse subject to a change in resistance through the controlled application of a programming current from a programming voltage source connected to a first terminal of the eFuse; a blow transistor formed on or over the substrate and having a control terminal configured to cause the programming current to flow through the eFuse in response to a programming signal; an intermediate transistor formed on or over the substrate and electrically coupled in series between a second terminal of the eFuse and the blow transistor; and, control circuitry formed on or over the substrate and electrically coupled to a node between the second terminal of the eFuse and the intermediate transistor, the control circuitry configured to reduce the flow of programming current through the eFuse in the event that a voltage detected at the node reaches a threshold level.

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

Abstract: A temperature sensing device for a temperature-based tamper detection system includes an integrated circuit (IC) and a logic circuit. The logic circuit sends an enable signal to the IC, causing it to measure the device temperature, and initiates a security timer. In response to not receiving the device temperature before the security timer expires, the logic circuit outputs a tamper event signal and an error code. The logic circuit can disable the enable signal in response to not receiving the device temperature before the timer expires. In some implementations, the logic circuit is a first logic circuit, and the IC includes an analog integrated circuit (AIC) and a second logic circuit. The second logic circuit receives the enable signal from the first logic circuit, causes the AIC to measure the device temperature, and outputs a ready signal and the device temperature to the first logic circuit.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.

Abstract: A clock generator includes a buffer stage to drive an output clock and a slew accelerator circuit to receive a first clock signal and generate an input clock signal to the buffer stage. The slew accelerator circuit includes first, second, and third inverter stages. The first stage generates a pair of non-overlapping clock signals from the first clock signal. A rise time of a first non-overlapping clock signal of the pair is faster than a rise time of a second non-overlapping clock signal of the pair, and a fall time of the second non-overlapping clock signal is faster than a fall time of the first non-overlapping clock signal. The second stage generates a first intermediate clock signal based on the pair of non-overlapping clock signals. The third stage generates the input clock signal to the buffer stage based on the first intermediate clock signal and the pair of non-overlapping clocks.