Abstract: A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.

Abstract: Systems and methods for controlled application of hysteresis in crystal oscillator circuits are discussed. In various embodiments, an Integrated Circuit (IC) may include: an inverter comparator coupled to a crystal oscillator, where the inverter comparator is configured to: (i) receive an input of the crystal oscillator, and (ii) output a clock signal; and a hysteresis control circuit coupled to the inverter comparator, wherein the inverter comparator is configured to: (i) start up with hysteresis disabled, and (ii) enable hysteresis in response to a hysteresis enable signal provided by the hysteresis control circuit.

Abstract: A device includes a hybrid puck corresponding to an electrostatic chuck. The hybrid puck includes a backing region and a chucking region disposed on the backing region. The backing region includes a first dielectric material to improve thermal performance of the hybrid puck. The chucking region includes a second dielectric material different from the first dielectric material to improve leakage current stability.

Abstract: An integrated circuit (IC), comprising a fuse structure (eFuse) formed in a resistive layer over a semiconductor substrate, the eFuse subject to a change in resistance through the controlled application of a programming current from a programming voltage source connected to a first terminal of the eFuse; a blow transistor formed on or over the substrate and having a control terminal configured to cause the programming current to flow through the eFuse in response to a programming signal; an intermediate transistor formed on or over the substrate and electrically coupled in series between a second terminal of the eFuse and the blow transistor; and, control circuitry formed on or over the substrate and electrically coupled to a node between the second terminal of the eFuse and the intermediate transistor, the control circuitry configured to reduce the flow of programming current through the eFuse in the event that a voltage detected at the node reaches a threshold level.

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

Abstract: A temperature sensing device for a temperature-based tamper detection system includes an integrated circuit (IC) and a logic circuit. The logic circuit sends an enable signal to the IC, causing it to measure the device temperature, and initiates a security timer. In response to not receiving the device temperature before the security timer expires, the logic circuit outputs a tamper event signal and an error code. The logic circuit can disable the enable signal in response to not receiving the device temperature before the timer expires. In some implementations, the logic circuit is a first logic circuit, and the IC includes an analog integrated circuit (AIC) and a second logic circuit. The second logic circuit receives the enable signal from the first logic circuit, causes the AIC to measure the device temperature, and outputs a ready signal and the device temperature to the first logic circuit.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.

Abstract: A clock generator includes a buffer stage to drive an output clock and a slew accelerator circuit to receive a first clock signal and generate an input clock signal to the buffer stage. The slew accelerator circuit includes first, second, and third inverter stages. The first stage generates a pair of non-overlapping clock signals from the first clock signal. A rise time of a first non-overlapping clock signal of the pair is faster than a rise time of a second non-overlapping clock signal of the pair, and a fall time of the second non-overlapping clock signal is faster than a fall time of the first non-overlapping clock signal. The second stage generates a first intermediate clock signal based on the pair of non-overlapping clock signals. The third stage generates the input clock signal to the buffer stage based on the first intermediate clock signal and the pair of non-overlapping clocks.

Abstract: A method for remote control of at least one non-ultra wide band (nUWB) device in a space by an electronic device is provided. The method includes identifying a position using at least one ultra wideband (UWB) anchor in the space, determining a field of view based on the position of the electronic device in the space, identifying the at least one nUWB device within the field of view, and establishing communication with the at least one nUWB device.

Abstract: Semiconductor manufacturing processing chambers with recycling capability and methods of recycling a chemical precursor are described. The processing chamber comprises a chamber body with a substrate support. The substrate support is spaced form the chamber lid to create a process region. A gas inlet provides a flow of gas to the process region and a recirculation plenum is in fluid communication with the process region. At least one fast-acting valve is connected to the recirculation plenum with a recirculation inlet line. A recirculation housing is in fluid communication with the recirculation inlet line and a recirculation outlet line. A recirculation piston valve allows a gas within the process chamber to be recycled into the original precursor container or into a different container for reuse.

Abstract: A circuit includes primary register circuitry to receive a first signal to write a first value to the primary register circuitry; secondary register circuitry to receive a second signal to write a second value to the secondary register circuitry; a counter configured to count a set amount of time from when the first signal is received; and a controller coupled to the counter. The controller receives at least one of: a third signal indicating whether the second signal was detected within the set amount of time, and a fourth signal indicating whether the first value is the same as the second value.

Abstract: An example apparatus includes clock divider circuitry configured to divide a system clock by a pre-scaler input to generate a divided clock; counter circuitry configured to increment a system count based on the divided clock; comparison circuitry configured to determine a count difference between the system count and a real-time clock count; and controller circuitry configured to modify the pre-scaler input based on a comparison of the count difference to a threshold value.

Abstract: Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses that may calibrate a resistor-capacitor (RC) circuit.

Abstract: The present disclosure encompasses solid state forms of Vericiguat, in embodiments crystalline polymorphs of Vericiguat, processes for preparation thereof, and pharmaceutical compositions thereof.

Abstract: The present invention relates to an anti-HIV recombinant HIV-1 derived Topoisomerase II? kinase. It inhibits HIV-1 replication by blocking viral entry. Its recognition by envelope antibodies ID6 and 4G10 makes it a justifiable immunogen for use as vaccine candidate in form of protein, mRNA and DNA vaccine against HIV infection. Thus, the protein, mRNA and DNA of immunogenic recombinant HIV-1 derived Topoisomerase II? kinase and derived peptides with and without spacers can be used as a HIV vaccine. FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16.

Abstract: Disclosed methods include initiating a system basic I/O system (BIOS) and, responsive to detecting an empty drive, accessing evaluating local BIOS telemetry data associated with installation of a new drive. Upon determining that the BIOS telemetry data a specified criteria, a long disk self-test (DST) and a short DST, may be performed. If the DSTs generate no hardware errors, hard drive service data including, for example, call log and service tag history associated with the information handling system, may be retrieved from a cloud backend to authorize an OS installation. Upon approving an OS installation, a service operating system (SOS) image may be retrieved from an OEM backend and a special key operable to cause a startup service of the SOS to boot to an os installation flow may be accessed from a firmware volume in SPI flash to enable the SOS to initiate an OS installation flow.

Abstract: Systems and methods for managing traffic in a hybrid environment include monitoring traffic load of a local network to determine whether the traffic load exceeds or is likely to exceed a maximum traffic load, where the maximum traffic load is a traffic load for which a service can be provided by the local network, based on a license. An excess traffic load is determined if the traffic load exceeds or is likely to exceed the maximum traffic load. One or more external networks which have a capacity to provide the service to the excess traffic load are determined, to which the excess traffic load is migrated. The local network includes one or more service instances for providing the service for up to the maximum traffic load, and the service to the excess traffic load is provided by one or more additional service instances in the one or more external networks.

Abstract: Systems or methods of the present disclosure may provide an integrated circuit system including data plane circuitry that includes a packet processing pipeline and extraction circuitry, wherein the extraction circuitry is configurable to extract one or more features of a packet via the packet processing pipeline. The integrated circuit system also includes inferencing circuitry configurable to perform machine learning inferencing based on the one or more features.

Abstract: Semiconductor processing systems and system components are described. The system components include a chamber lid of a semiconductor processing chamber that includes a dielectric material having a substantially disk shape and integrating a lid portion and a gas delivery nozzle portion into a single structure. The chamber lid includes a plurality of gas flow paths that each traverse a region of the chamber lid from an input location at a first surface of the chamber lid to a respective output location on a different surface of the chamber lid and through which etch gases are distributed to particular portions of a processing region of the processing chamber.

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.