Abstract: Distributed execution of transactions may be performed across shards of a scalable database table. Instructions to perform as part of a transaction with respect to one or more database tables may be received. The instructions may be evaluated with respect to metadata obtained for the database tables to determine an assignment distribution of computing resources of the database system to data that can satisfy the access request. The commit protocol for the transaction may be determined according to the assignment distribution of the computing resources. After a request to commit the transaction is received, the transaction may be committed according to the determined commit protocol.

Abstract: A single stage electromagnetic interference (EMI) filter circuit includes a power source input configured to connect to a power source; an equivalent common mode and differential mode filter including a single inductor having both common mode inductance for common mode filtering and specific parasitic inductance; and a differential capacitance stage connected to the single inductor in parallel, wherein a combination of the specific parasitic inductance and capacitance of the differential capacitance stage are used to provide differential mode filtering.

Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.

Abstract: A method for tracking and measuring body flexibility and balance of a user during physical activity is provided. The method includes capturing sensor data from a plurality of wearable devices for tracking and determining body posture, analyzing the captured sensor data to determine a plurality of parameters including information related to body posture and physical metrics including balance and flexibility, and displaying a balance score, a flexibility score, and transition over time based on the analysis.

Abstract: Methods and systems are herein provided for determining operating conditions of a magnetic resonance (MR) scanner based on data of one or more implants of a patient and storing the data of the one or more implants are provided. In one examples, a method comprises obtaining data of one or more implants of a patient from one or more sources; determining one or more configurations of each of the one or more implants; displaying, via a graphical user interface (GUI), the data and the one or more configurations; determining a recommendation configuration based on the one or more configurations; determining a selected configuration via user input to the GUI; and determining operating conditions of an MRI scanner based on the selected configuration for an MRI exam.

Abstract: Techniques and apparatus for swapping a primary power source (e.g., a main battery) while using a secondary power source (e.g., a backup battery or a supercapacitor) to power a portable device. One example integrated circuit (IC) for power management generally includes a first power supply node; a second power supply node; a first port for coupling to a primary power source; a first switch coupled between the first power supply node and the first port; a second port for coupling to a secondary power source; a second switch coupled between the first power supply node and the second port; and a third switch coupled between the first and second power supply nodes. For certain aspects, the IC also includes a third power supply node, a voltage regulator coupled between the first and third power supply nodes, and a fourth switch coupled between the second and third power supply nodes.

Abstract: A carbazate-functional compound includes a plurality of groups having the following structure: [formula (I)] where X forms at least a portion of: a urethane linkage, an ester linkage, or an ether linkage. At least one R1 from the plurality of groups is free of a hydroxyl-functional group.

Abstract: A compensation system for a crystal oscillator including a DC level comparator, current compensation circuitry, and a compensation controller. The crystal oscillator includes an amplifier with a feedback resistance coupled between first and second terminals of a crystal resonator. The DC level comparator may be a hysteretic comparator that compares a DC level of the first node with a DC level of the second node and to provide a corresponding compensation signal. The compensation controller controls a magnitude and direction of the compensation current applied to the first node by the current compensation circuitry based on the compensation signal. The current compensation circuitry sources current to or sinks current from the first node until the leakage current is minimized. The compensation controller may include a digital counter the generates a digital control value used to activate selected current sources or sinks for developing the compensation current.

Abstract: An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.

Abstract: A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to protect against voltage glitch attacks in microcontrollers. An example apparatus includes logic circuitry operable to, in response to a voltage glitch, pause processing circuitry; number generator circuitry operable to generate a number; a counter operable to, after the voltage glitch ends, adjust a count corresponding to the number; and the logic circuitry operable to unpause the processing circuitry after the count reaches a value.

Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.

Abstract: Systems and methods for controlled application of hysteresis in crystal oscillator circuits are discussed. In various embodiments, an Integrated Circuit (IC) may include: an inverter comparator coupled to a crystal oscillator, where the inverter comparator is configured to: (i) receive an input of the crystal oscillator, and (ii) output a clock signal; and a hysteresis control circuit coupled to the inverter comparator, wherein the inverter comparator is configured to: (i) start up with hysteresis disabled, and (ii) enable hysteresis in response to a hysteresis enable signal provided by the hysteresis control circuit.

Abstract: In an example, a device includes a controller and a direct current (DC)-to-DC converter coupled to the controller and configured to provide a load current to a load. The device also includes a low-dropout (LDO) regulator coupled to the DC-to-DC converter. The controller includes digital logic, and the digital logic is configured to determine the load current. The digital logic is configured to turn on the LDO regulator if the load current is above a predetermined threshold. The digital logic is also configured to turn off the LDO regulator if the load current is below the predetermined threshold.

Abstract: A video headset comprises a left earphone assembly, a right earphone assembly, and a headband assembly having a headband frame. The headband frame comprises a left end portion movably coupled to the left earphone assembly and a right end portion movably coupled to the right earphone assembly. The headset comprises a video screen module connected to each earphone assembly via a boom module. The video screen module comprises video screens including a first video screen and a second video screen pivotally connected to a second video screen. The second video screen faces in an opposite direction from the first video screen. The headset enables to stream both audio and video data at the video screen module. The headset is further configured to connect with external devices and stream data from different external devices on different video screens. The headset has multiple cameras on the headset to enable 360 degree viewing.

Abstract: A method for quadrature phase shifted clock generation with duty cycle correction includes A reference clock is delayed with a delay circuit to generate a delayed clock, wherein a delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock comprise a plurality of states comprising a first state and a second state. A first edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. A second edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. The control value is driven to the first edge value during the second state of the delayed clock and to the second edge value during the first state of the delayed clock.

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

Abstract: A network-communicating device with a signal input adapted to receive a sensor-derived signal; an analog-to-digital converter (ADC) having an input coupled to the signal input and an output; a data scrambling circuit having an input coupled to the output of the ADC and an output; a watermark insertion circuit having an input coupled to the output of the data scrambling circuit and an output; and a signal output coupled to the output of the watermark insertion circuit.

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

Abstract: The disclosed technology relates to improved user authentication to verify transaction legitimacy. An exemplary system may send a request for a current image to a mobile device associated with a user. The request may include an indication of a requested action to be performed by the user. The system may classify an action depicted in the current image obtained in response to the request. A determination may be made as to whether the depicted action corresponds to the requested action based on the classification. When it does correspond, the system may compare facial feature(s) recognized in obtained past image(s) associated with the user to a facial feature(s) recognized in the current image to determine when the user is depicted in both the past image(s) and the current image. When the user is depicted in both the past image(s) and the current image, the system may allow the transaction to proceed.