Abstract: The present disclosure encompasses solid state forms of Vericiguat, in embodiments crystalline polymorphs of Vericiguat, processes for preparation thereof, and pharmaceutical compositions thereof.

Abstract: The present invention relates to an anti-HIV recombinant HIV-1 derived Topoisomerase II? kinase. It inhibits HIV-1 replication by blocking viral entry. Its recognition by envelope antibodies ID6 and 4G10 makes it a justifiable immunogen for use as vaccine candidate in form of protein, mRNA and DNA vaccine against HIV infection. Thus, the protein, mRNA and DNA of immunogenic recombinant HIV-1 derived Topoisomerase II? kinase and derived peptides with and without spacers can be used as a HIV vaccine. FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16.

Abstract: Semiconductor processing systems and system components are described. The system components include a chamber lid of a semiconductor processing chamber that includes a dielectric material having a substantially disk shape and integrating a lid portion and a gas delivery nozzle portion into a single structure. The chamber lid includes a plurality of gas flow paths that each traverse a region of the chamber lid from an input location at a first surface of the chamber lid to a respective output location on a different surface of the chamber lid and through which etch gases are distributed to particular portions of a processing region of the processing chamber.

Abstract: Various examples disclosed herein relate to digital signal processing, and more particularly, to identifying metrics of audio samples to dynamically adjust the gain of audio data. In an example embodiment, a pulse density modulation system is provided that includes sample generation circuitry and gain control circuitry coupled to the sample generation circuitry. The sample generation circuitry is configured to sample audio data to produce samples of the audio data and output the samples to a processor and to the gain control circuitry. The gain control circuitry is configured to determine one or more metrics based on the samples of the audio data and output the one or more metrics to the processor.

Abstract: Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically to generating a clock signal at desired frequencies based on inputs to a clock subsystem for peripheral use. A clock subsystem is provided herein that comprises an oscillator configured to provide a clock signal at either a first frequency or a second frequency, and a controller coupled to the oscillator and configured to perform various functions. The controller can be configured to determine a desired frequency of the clock signal based on a state of each input of multiple inputs, wherein the multiple inputs comprise a power mode input and an analog-to-digital converter input, and provide a signal to the oscillator to produce the clock signal at the desired frequency.

Abstract: Techniques and apparatus for swapping a primary power source (e.g., a main battery) while using a secondary power source (e.g., a backup battery or a supercapacitor) to power a portable device. One example integrated circuit (IC) for power management generally includes a first power supply node; a second power supply node; a first port for coupling to a primary power source; a first switch coupled between the first power supply node and the first port; a second port for coupling to a secondary power source; a second switch coupled between the first power supply node and the second port; and a third switch coupled between the first and second power supply nodes. For certain aspects, the IC also includes a third power supply node, a voltage regulator coupled between the first and third power supply nodes, and a fourth switch coupled between the second and third power supply nodes.

Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.

Abstract: First images that are screenshots from a first version of a software component are obtained. Second images that are screenshots from a second version are obtained. A collection of image deviations that includes pair-wise image deviations between pairs of images are identified. A pair of images includes a first image from the first images and a corresponding second image from the second images. An image deviation indicates a portion of the second image identified as differing from a spatially corresponding portion of the first image. The image deviations are grouped into deviation groups. At least some of the second images are associated with at least some of the deviation groups. A subset of the second images corresponding to a deviation group is output responsive to a selection of an indication of the deviation group.

Abstract: An enclosure assembly includes a housing defining an interior configured to at least partially house one or more electrical components. The housing includes a housing section including an outer plastic portion and an inner metal portion received in the outer plastic portion. An electrical component disposed within the housing section provides power to at least one other electrical component.

Abstract: An electrostatic chuck (ESC) having a ceramic body including embedded electrodes and having a first diameter. Three or more regions are defined on a surface and arranged concentrically on the surface, each region includes a retaining ring arranged on the surface and defining an outer edge of the region, and supportive structures arranged on the surface and within the region. The supportive structures are configured to support a surface of a substrate when the substrate is retained by the ESC. The ESC includes conduits formed in the ceramic body and configured to independently introduce a gas into each region through the ceramic body and to the first surface. Each region is configured to retain a corresponding positive gas pressure within the region and the surface of the substrate, and the one or more embedded electrodes are configured to generate a retaining force on the surface of the substrate.

Abstract: Mechanisms to place flip-flops and other synchronous logic cells in a circuit layout in a clock on-chip variation-aware, predetermined order based on analysis of the clock gating, connectivity, and logic depth of the unplaced netlist. The resulting placements enable clock trees having a regular structure leading to improvements in clock on-chip variation, timing, and clock power.

Abstract: Techniques are described for an adaptive CoPP that can adapt and change based on actual network control traffic rather than static CoPP rates. An aggressive CoPP can protect the CPU (route processor) of a network device, e.g., routers and switches, but may also penalize convergence and performance. An adaptive CoPP may protect CPU as well as boost convergence and performance parameters. In particular, traffic between two sites may be managed by proactively changing the thresholds of lower CoS traffic based on the CoPP utilization of various protocol/BPDU class traffic, thereby improving data plane convergence and application performance in scaled environments.

Abstract: Systems and methods for adjusting for delay asymmetry between clocks in a communication network. Disclosed systems and methods may adjust data in one or more Sync and Delay Response Messages sent using the Precision Timing Protocol (PTP) based on one or more averages made of timing information in those Sync and Delay Response Messages.

Abstract: An example apparatus includes clock divider circuitry configured to divide a system clock by a pre-scaler input to generate a divided clock; counter circuitry configured to increment a system count based on the divided clock; comparison circuitry configured to determine a count difference between the system count and a real-time clock count; and controller circuitry configured to modify the pre-scaler input based on a comparison of the count difference to a threshold value.

Abstract: A system 10 to optimize a light emitting diode (LED) power allocation framework within a room is disclosed. The system 10 includes a data receiving subsystem 20, configured to receive parameters corresponding to light emitting diodes (LED), visible light communication (VLC) transmitters and visible light communication (VLC) receivers. The system 10 includes a blockage generalization subsystem 22, configured to identify location and height of one or more detected blockages within the room from the received parameters. The system 10 includes an optimal power allocation subsystem 24, configured to compute a visible light communication (VLC) channel gain for each of the one or more light emitting diodes (LED) with reference to identified location and identified height and configured to optimize the power allocation framework to achieve maximized visible light communication (VLC) data rate based on the computed visible light communication (VLC) channel gain and one or more constraints.

Abstract: A circuit includes a primary register region and a primary shadow register; a secondary register region and a secondary shadow register; and a safety controller having multiple states. The safety controller transitions to a first write state when a first write signal to write a first value to the primary register region is detected, and copies the first value written to the primary register region to the primary shadow register; transitions to a second write state when a second write signal to write a second value to the secondary register region is detected within a set amount of time of detection of the first write signal, and in the second write state, copies the second value written to the secondary register region to the secondary shadow register; transitions to a compare state to receive a comparison signal indicating whether the first value is the same as the second value; and transitions to an update state when the first value is the same as the second value.

Abstract: In an example, a voltage converter includes a pulse generator. The voltage converter also includes a high-side transistor having a gate coupled to the pulse generator, a source coupled to a first voltage terminal, and a drain coupled to an output node. The voltage converter includes a low-side transistor having a gate coupled to the pulse generator, a source coupled to a second voltage terminal, and a drain coupled to the output node. The voltage converter includes a charge lookup table coupled to the pulse generator, where the charge lookup table is configured to provide a charge duration. The voltage converter includes a discharge lookup table coupled to the pulse generator, where the discharge lookup table is configured to provide a discharge duration. The voltage converter also includes a latch coupled to the charge lookup table, where the latch is configured to store an indication of a supply voltage.

Abstract: Apparatuses for substrate transfer are provided. A lift pin assembly can include a lift pin, a purge cylinder, and a lift pin guide. The lift pin guide is disposed adjacent the purge cylinder. The lift pin guide and the purge cylinder have a passage formed therethrough in which the lift pin is disposed. The purge cylinder includes one or more nozzles that direct the flow of gas radially inward into a portion of the passage disposed in the purge cylinder. The one or more nozzles are disposed radially outward from the lift pin. The purge cylinder reduces particle deposition on the substrate by preventing contact between the lift pin and the support assembly as the lift pin is in motion.

Abstract: An integrated circuit includes a semiconductor substrate patterned to include a first semiconductor track and a second semiconductor track separated from each other by a trench isolation region. The integrated circuit includes a logic circuit including a transistor having a first drain subregion in the first semiconductor track, a second drain subregion in the second semiconductor track, a first source subregion in the first semiconductor track, and a second source subregion in the second semiconductor track. A diffusion bridge of semiconductor material extends between the first and second semiconductor tracks and connects the first source subregion to the second source subregion. The first drain subregion and the second drain subregion are electrically connected by a drain metalization.

Abstract: A system 10 to optimize a light emitting diode (LED) power allocation framework within a room is disclosed. The system 10 includes a data receiving subsystem 20, configured to receive parameters corresponding to light emitting diodes (LED), visible light communication (VLC) transmitters and visible light communication (VLC) receivers. The system 10 includes a blockage generalization subsystem 22, configured to identify location and height of one or more detected blockages within the room from the received parameters. The system 10 includes an optimal power allocation subsystem 24, configured to compute a visible light communication (VLC) channel gain for each of the one or more light emitting diodes (LED) with reference to identified location and identified height and configured to optimize the power allocation framework to achieve maximized visible light communication (VLC) data rate based on the computed visible light communication (VLC) channel gain and one or more constraints.