Abstract: An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC toa second digital conversion output from the ADC.

Abstract: This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

Abstract: A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

Abstract: Systems and methods applicable to generating management decisions for online advertising. Machine learning models, including reinforcement learning-based machine learning models, can be utilized in making various advertising management decisions.

Abstract: Techniques including receiving a first control value, starting a timeout counter based on receiving the first control value, receiving a second control value, determining whether the second control value is received before the timeout counter expires, and based on the determination that the second control value is received before the timeout counter expires: determining whether the first control value is the same as the second control value, and loading the first control value into a set of control registers based on the determination that the first control value is the same as the second control value.

Abstract: An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC to a second digital conversion output from the ADC.

Abstract: Embodiments determine mismatches in evaluations. Embodiments receive a first evaluation of an employee from a supervisor of the employee, the first evaluation including supervisor comment ratings and supervisor numerical ratings, each of the supervisor comment ratings and supervisor numerical ratings corresponding to an evaluation category. Embodiments receive a second evaluation of the employee from the employee, the second evaluation including employee comment ratings and employee numerical ratings, each of the employee comment ratings and employee numerical ratings corresponding to the evaluation category. Embodiments determine first sentiment polarity scores of the supervisor comment ratings and second sentiment polarity scores of the employee comment ratings.

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block.

Abstract: Subject matter disclosed herein may relate to reconstructing wireless signal packets and may relate more particularly to reconstructing wireless signal packets from iterations of the wireless signal packets repeatedly transmitted by a transmitter device.

Abstract: A computer-implemented method comprises generating computer executable code as one or more code portions; detecting a number of processing operations required to reach one or more predetermined stages in execution of each code portion; and associating with each code portion one or more progress indicators, each representing a respective execution stage of the one or more predetermined stages within execution of that code portion. The code portions are executed by a processor powered by an unpredictable power source. When the processor detects an energy condition indicating that no more than a reserve quantity of electrical energy is available, the progress indicators are used to determine whether or not to perform a checkpoint.

Abstract: The present disclosure describes techniques for performing a smart tree lookup operation in a balanced tree. The techniques according to the present disclosure comprise identifying at least one data entry to be searched within the balanced tree, extracting a plurality of keys of the balanced tree, determining whether all or a subset of keys of the plurality of keys are required for searching the at least one data entry within the balanced tree, in response to the determination that the subset of keys of the plurality of keys are required for searching the at least one data entry, generating a first compare function for each of the at least one data entry using the subset of keys, and traversing a first path for the at least one data entry based on the first compare function. Accordingly, the techniques of the present disclosure enable efficient balanced tree lookup operation.

Abstract: The present disclosure provides an optical fibre. The optical fibre includes a core, an inner cladding, a first trench region, an intermediate cladding, a second trench region, and an outer cladding. The core has a first radius. The inner cladding is defined by the first radius and a second radius of the optical fibre. The first trench region is defined by the second radius and a third radius. The first trench region. The intermediate cladding is defined by the third radius and a fourth radius. The second trench region is defined by the fourth radius and a fifth radius. The outer cladding is defined by the fifth radius and a sixth radius.

Abstract: Techniques are described for an adaptive CoPP that can adapt and change based on actual network control traffic rather than static CoPP rates. An aggressive CoPP can protect the CPU (route processor) of a network device, e.g., routers and switches, but may also penalize convergence and performance. An adaptive CoPP may protect CPU as well as boost convergence and performance parameters. In particular, traffic between two sites may be managed by proactively changing the thresholds of lower CoS traffic based on the CoPP utilization of various protocol/BPDU class traffic, thereby improving data plane convergence and application performance in scaled environments.

Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.

Abstract: The present disclosure provides an optical fibre. The optical fibre includes a core extended from a central longitudinal axis to a first radius r1. Further, the optical fibre includes a first trench region extended from a second radius r2 to a third radius r3, a second trench region extended from the third radius r3 to a fourth radius r4 and a cladding region extended from the fourth radius r4 to a fifth radius r5.

Abstract: A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.

Abstract: An aircraft structure protected from collisions with foreign objects includes a first support proximate to an aircraft structure root; first sheets attached to the first support to form a first leading edge portion of the aircraft structure; a second support proximate to an outer end of the aircraft structure; second sheets attached to the second support to form a second leading edge portion; and a door including one or more ribs disposed between the first and second supports and configured to give shape to a third leading edge portion of the aircraft structure; and third sheets, attached to the ribs to form the third portion of the leading edge; wherein the first support, the first sheets, the second support, the second sheets, the one or more ribs, and the third sheets are disposed to mitigate damage from a foreign object collision by absorbing kinetic energy from a collision.

Abstract: Subject matter disclosed herein may relate to wireless energy harvesting devices and may relate more particularly to system-on-a-chip testing for wireless energy harvesting devices.

Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.