Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block.

Abstract: An example apparatus includes clock divider circuitry configured to divide a system clock by a pre-scaler input to generate a divided clock; counter circuitry configured to increment a system count based on the divided clock; comparison circuitry configured to determine a count difference between the system count and a real-time clock count; and controller circuitry configured to modify the pre-scaler input based on a comparison of the count difference to a threshold value.

Abstract: A circuit includes a primary register region and a primary shadow register; a secondary register region and a secondary shadow register; and a safety controller having multiple states. The safety controller transitions to a first write state when a first write signal to write a first value to the primary register region is detected, and copies the first value written to the primary register region to the primary shadow register; transitions to a second write state when a second write signal to write a second value to the secondary register region is detected within a set amount of time of detection of the first write signal, and in the second write state, copies the second value written to the secondary register region to the secondary shadow register; transitions to a compare state to receive a comparison signal indicating whether the first value is the same as the second value; and transitions to an update state when the first value is the same as the second value.

Abstract: An access network can include a plurality of remote nodes connected to a principal controller. The principal controller can experience an event storm when one or more of the plurality of remote nodes report an access network event at the same or substantially the same time. One or more remote nodes can mitigate such an event storm at the principal core by delaying by an event reporting delay the reporting of the access network event to the principal core. The event reporting delay can be based on an event delay policy associated with a given remote node. The even reporting delay can be different for each remote node or a group of remote nodes so that the principal core does not receive reports from the plurality of remote nodes so as to cause an event storm which can negatively impact the access network, one or more network devices, or both.

Abstract: In an example, a device includes a controller and a direct current (DC)-to-DC converter coupled to the controller and configured to provide a load current to a load. The device also includes a low-dropout (LDO) regulator coupled to the DC-to-DC converter. The controller includes digital logic, and the digital logic is configured to determine the load current. The digital logic is configured to turn on the LDO regulator if the load current is above a predetermined threshold. The digital logic is also configured to turn off the LDO regulator if the load current is below the predetermined threshold.

Abstract: In described examples, an integrated circuit (IC) includes a first temperature sensor, a processor, a second temperature sensor, and a reset module. The first sensor senses a first body temperature of the IC. The processor asserts a thermal shutdown signal if the first body temperature exceeds a first threshold. In response to the thermal shutdown signal, the second sensor asserts a reset request signal and senses a second body temperature of the IC. If the second body temperature is less than a second threshold, the second sensor asserts a reset end signal. The reset module outputs a system reset signal to the first sensor and the processor if the reset request signal is asserted, and outputs a system recovery signal if the reset end signal is asserted. The first sensor and the processor deactivate if the system reset signal is asserted, and activate if the system recovery signal is asserted.

Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.

Abstract: A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.

Abstract: Techniques for allocating channel frequencies in remote physical device. The channel frequencies are sorted in a predefined order, wherein each channel frequency has a symbol rate. Further, the channel frequencies are grouped into one or more channel groups, wherein each channel group comprises one or more channel frequencies. The one or more channel groups are prioritized from highest priority to lowest priority. Further, the one or more channel frequencies are allocated starting from highest priority channel group to largest size window based on available slots in the largest size window and till a difference between last channel frequency and first channel frequency falls within frequency span limit of the largest size window. Further, prioritizing and allocating are repeated till remaining one or more channel frequencies of the one or more channel groups are allocated to next available windows or the next available windows are exhausted.

Abstract: A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.

Abstract: This disclosure relates to a system that includes a centralized trim controller and a non-volatile memory that includes a trim sector configured for hosting trim data for one or more peripherals. The trim controller is configured to receive, for each of the one or more peripherals, trim values of the one or more peripherals from the trim sector of the nonvolatile memory, and provide the trim values to the one or more peripherals. Some trim values are updateable by receiving a password at the trim controller. If the password is valid, a timeout counter is initiated, during which time the trim value is updateable.

Abstract: The disclosed technology relates to improved user authentication to verify transaction legitimacy. An exemplary system may send a request for a current image to a mobile device associated with a user. The request may include an indication of a requested action to be performed by the user. The system may classify an action depicted in the current image obtained in response to the request. A determination may be made as to whether the depicted action corresponds to the requested action based on the classification. When it does correspond, the system may compare facial feature(s) recognized in obtained past image(s) associated with the user to a facial feature(s) recognized in the current image to determine when the user is depicted in both the past image(s) and the current image. When the user is depicted in both the past image(s) and the current image, the system may allow the transaction to proceed.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.

Abstract: A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.

Abstract: An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data.

Abstract: A simulator extracts sensor data from multiple systems. The sensor data includes measurements taken by sensors disposed at the multiple systems. The simulator standardizes the sensor data into a common format and classifies the sensor data according to a performance metric. A model of a target system for the performance metric is generated based on the standardized sensor data. The simulator can simulate the impact on the performance metric for a target system based on a simulated change to the multiple systems. The simulator can generate a network interface including a tool that enables end users to interact with the simulation and to determine procedures for mitigating the impact.

Abstract: A system and method for monitoring the health of a heater connected to a power supply by first and second power leads which conduct an inlet and outlet current, respectively. The system includes an injection transformer with a number of primary turns that are inductively coupled to the first power lead, a signal generator configured to generate and supply a time-varying injection signal to the primary turns thereby imposing the time-varying injection signal on the inlet current, and a signal reader configured to receive a diagnostic signal from the heater, filter the diagnostic signal to pass a frequency associated with the time-varying injection signal, and produce a heater capacitance signal that is indicative of a capacitance value of the heater, where the heater capacitance signal is indicative of the health of the heater.

Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.

Abstract: Disclosed are methods, systems and devices for varying operations of a transponder device based, at least in part, on an availability of energy and/or power that may be harvested and/or collected. In one particular implementation, operations to generate one or more signals from sensor circuitry and/or to perform computations may be varied based, at least in part, on an availability of harvestable and/or collectable energy and/or power.

Abstract: A method is provided. In some examples, the method includes receiving, at a sequencer circuit of an analog-to-digital converter (ADC), a first request to perform a first conversion. In addition, the method includes determining, by the sequencer circuit, that the ADC is not busy. The method further includes responsive to determining that the ADC is not busy, and by the sequencer circuit, causing the ADC to perform the first conversion. The method also includes receiving, at the sequencer circuit, a second request to perform a second conversion. The method includes determining, by the sequencer circuit, that the ADC is busy and, responsive to determining that the ADC is busy, and by the sequencer circuit, waiting to cause the ADC to perform the second conversion.