Abstract: Described herein are techniques related one or more systems, apparatuses, methods, etc. for reducing induced currents in a apparatus chassis. For example, a fractal slot is constructed in the apparatus chassis to reduce the induced currents, and enhance passage of magnetic fields through the apparatus chassis. In this example, the fractal slot may include a no-self loop fractal space filling curve shape to provide high impedance to the induced currents.

Abstract: This document discloses one or more systems, apparatuses, methods, etc. for integrating a spiral near field communications (NFC) coil antenna to a portable device for consistent coupling with different tags and devices.

Abstract: Described herein are techniques related one or more systems, apparatuses, methods, etc. for integrating a near field communications (NFC) coil antenna in a portable device. For example, the NFC antenna is integrated under a metal chassis of the portable device. The metal chassis and a conductive coating—that is integrated underneath the full metal chassis—are designed to include one or more slots to provide high impedance to Eddy current induced in the conductive coating.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron-doped germanium-tin alloy layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors). The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: A signal feed apparatus for an antenna including a slot through a conductive wall, comprises a non-conductive slot insert, a non-conductive block fixed to the slot insert and including first and second cable conduits and first and second plug sockets coinciding with first and second signal feed-points of the antenna. A signal cable is inserted into the cable conduits and includes first and second conductors. Conductive plugs are inserted into the first and second plug sockets to electrically connect the conductors to the first and second signal feed-points.

Abstract: Systems and methods are provided for authoring a web page template. A software code authoring tool is provided that enables authoring of source code that defines a Web site template. An improved template design and content management solution is provided that enables a user-friendly way for an author to create a web page template from a pre-existing output presentation. For instance, an authoring tool enables the author to designate what regions in a pre-existing web page are to be editable in a template created from the web page, wherein the editable regions of the template may be edited by a user interacting with an authoring tool.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: Described herein are techniques related to near field coupling and wireless power transfers. A mobile device may include an edge-emitting antenna that offers ultra slim, all-metallic chassis packaging option with no cutout, uses lesser area, has robust mechanical strength, and provides EMI/ESD protection. In one example, an inductor coil is wrapped around a magnetic core and a pair of conductive layers is configured to interpose the magnetic core and the inductor coil between them to expose an edge of the magnetic core. The inductor coil being operable in a transmit mode to generate a magnetic field in response to a current passing through it. The edge is configured to enhance outward radiation of the magnetic field. Based on simulation results, the edge-emitting antenna occupies less space and provides an acceptable level of performance for coupling coefficients compared to conventional antenna.

Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

Abstract: Systems and techniques for managing the use of almost blank subframes in wireless communication systems. Base stations in a wireless network monitor load information affecting network nodes. Load information may be in the form of load metric information. The load information may be exchanged between system elements, and an almost blank subframe proportioning may be updated by one or more of the base stations, and information relating to the updated proportioning. The updated almost blank subframe proportioning may be used in scheduling and load metric calculation, as well as almost blank subframe patterning. Updating of almost blank subframe information and load metric information may be performed iteratively.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

Abstract: Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures.

Abstract: Systems and methods for providing anti-malware protection on storage devices are described. In one embodiment, a storage device includes a controller, firmware, and memory. The firmware communicates with an authorized entity (e.g., external entity, operating system) to establish a secure communication channel. The system includes secure storage to securely store data.

Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibit reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: A steam reformer may comprise fluid inlet and outlet connections and have a substantially cylindrical geometry divided into reforming segments and reforming compartments extending longitudinally within the reformer, each being in fluid communication. With the fluid inlets and outlets. Further, methods for generating hydrogen may comprise steam reformation and material adsorption in one operation followed by regeneration of adsorbers in another operation. Cathode off-gas from a fuel cell may be used to regenerate and sweep the adsorbers, and the operations may cycle among a plurality of adsorption enhanced reformers to provide a continuous flow of hydrogen.

Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstained channel structures.

Abstract: A near-horizon antenna structure includes an upper radiating element having a straight conductive trace disposed on a planar surface of a non-conductive substrate, a rectangular lower radiating element serving as a ground plane disposed on the planar surface, and a feed point provided between the upper and lower radiating elements. When the planar surface is positioned vertically, the far-field effects of horizontal current flowing in opposite directions on the radiating elements cancel to provide an antenna pattern with increased gain in horizontal directions and reduced gain in vertical directions. A flat panel display and a portable communication device are also provided with one or more near-horizon antenna structures integrated therein.