Abstract: Methods and systems are described for filtering out signal strength data associated with access points and a client device using heuristic and intra-access point analysis. The filtered data may be used to approximate the location of the client device. By filtering signal strength values through a heuristic and intra-access point analysis; the systems and methods described eliminate inaccurate or anomalistic values, which may negatively alter the estimated location of the client device. Accordingly, the systems and methods may produce more accurate client device location estimates by intelligently examining detected signal strength values.

Abstract: A system and method is described that computes an estimated current location for a client device based on both the detected current location and the predicted current location of the client device. By utilizing the predicted current location, the system and method may account for and compensate for anomalies and inaccuracies in the detected current location. Accordingly, the system and method provides a more accurate estimation for the current location of the client device based on examination of heuristics and a priori environmental data. In particular, the system and method compensates for detected locations that are impossible or improbable based on previous locations of the client device, the layout of the environment in which the client device is traversing, data describing the user of the client device, and/or data describing the client device.

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

Abstract: Techniques for enabling real-time enterprise workforce management over a telecom network are provided. The techniques include receiving real-time workforce information from one or more telecom networks, and using the real-time information for dynamic load optimization to enable real-time enterprise workforce management.

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

Abstract: A system and method is described that computes an estimated current location for a client device based on both the detected current location and the predicted current location of the client device. By utilizing the predicted current location, the system and method may account for and compensate for anomalies and inaccuracies in the detected current location. Accordingly, the system and method provides a more accurate estimation for the current location of the client device based on examination of heuristics and a priori environmental data. In particular, the system and method compensates for detected locations that are impossible or improbable based on previous locations of the client device, the layout of the environment in which the client device is traversing, data describing the user of the client device, and/or data describing the client device.

Abstract: A Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an N-type substrate and an epitaxial structure on a front-side of the N-type substrate. The epitaxial substrate includes a P-type layer adjacent to the N-type substrate and one or more additional SiC layers on the P-type layer opposite the N-type substrate. The semiconductor device also includes one or more openings through the N-type substrate that extend from a back-side of the N-type substrate to the P-type layer and a back-side contact on the back-side of the N-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the N-type substrate.

Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

Abstract: A system and method is described that computes an estimated current location for a client device based on both the detected current location and the predicted current location of the client device. By utilizing the predicted current location, the system and method may account for and compensate for anomalies and inaccuracies in the detected current location. Accordingly, the system and method provides a more accurate estimation for the current location of the client device based on examination of heuristics and a priori environmental data. In particular, the system and method compensates for detected locations that are impossible or improbable based on previous locations of the client device, the layout of the environment in which the client device is traversing, data describing the user of the client device, and/or data describing the client device.

Abstract: Methods and systems are described for filtering out signal strength data associated with access points and a client device using heuristic and intra-access point analysis. The filtered data may be used to approximate the location of the client device. By filtering signal strength values through a heuristic and intra-access point analysis; the systems and methods described eliminate inaccurate or anomalistic values, which may negatively alter the estimated location of the client device. Accordingly, the systems and methods may produce more accurate client device location estimates by intelligently examining detected signal strength values.

Abstract: Disclosed are systems, apparatus, and methods for integrating an information feed. In various implementations, an identity of a user may be determined based on authentication information, where the authentication information identifies a user profile. In some implementations, profile information is identified based on the determined identity, where the profile information identifies one or more entities tracked using one or more information feeds associated with the user profile, and where the one or more information feeds comprises one or more feed items stored in a database system. In various implementations, the identified profile information is associated with a user account provided by a network communications application.

Abstract: A vertically oriented field effect device has a body and an enhance gate structure. The body includes a JFET (junction field effect transistor) region disposed between junction implants that extend into the body from a top surface of the body. The gate structure includes a supplemental gate dielectric, a primary gate dielectric, and a gate contact. The supplemental gate dielectric is formed over the top surface of the body above the JFET region, such that the supplemental dielectric is separated from the junction implants by a gap. The primary gate dielectric is formed over the supplemental gate dielectric, above the gap over the top surface of the body, and over at least a portion of the junction implants. The gate contact is formed over the primary gate dielectric.

Abstract: A system for treating an aneurysm comprises an elongate flexible shaft and an expandable member. An expandable scaffold is disposed over the expandable member and may be expanded from a collapsed configuration to an expanded configuration. A double-walled filling structure is disposed over the scaffold and has an outer wall and an inner wall. The filling structure is adapted to be filled with a hardenable fluid filing medium so that the outer wall conforms to an inside surface of the aneurysm and the inner wall forms a substantially tubular lumen to provide a path for blood flow. In the expanded configuration the scaffold engages the inner wall of the filling structure. A tether is releasably coupled with the filling structure and the flexible shaft thereby constraining axial movement of the structures relative to each other.

Abstract: Methods of forming a power semiconductor device having an edge termination are provided in which the power semiconductor device that has a drift region of a first conductivity type is formed on a substrate. A junction termination extension is formed on the substrate adjacent the power semiconductor device, the junction termination extension including a plurality of junction termination zones that are doped with dopants having a second conductivity type. The junction termination zones have different effective doping concentrations. A dopant activation process is performed to activate at least some of the dopants in the junction termination zones. An electrical characteristic of the power semiconductor device is measured. Then, the junction termination extension is etched in order to reduce the effective doping concentration within the junction termination extension.

Abstract: Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.

Abstract: Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.

Abstract: A Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an N-type substrate and an epitaxial structure on a front-side of the N-type substrate. The epitaxial substrate includes a P-type layer adjacent to the N-type substrate and one or more additional SiC layers on the P-type layer opposite the N-type substrate. The semiconductor device also includes one or more openings through the N-type substrate that extend from a back-side of the N-type substrate to the P-type layer and a back-side contact on the back-side of the N-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the N-type substrate.

Abstract: A vertically oriented field effect device has a body and an enhance gate structure. The body includes a JFET (junction field effect transistor) region disposed between junction implants that extend into the body from a top surface of the body. The gate structure includes a supplemental gate dielectric, a primary gate dielectric, and a gate contact. The supplemental gate dielectric is formed over the top surface of the body above the JFET region, such that the supplemental dielectric is separated from the junction implants by a gap. The primary gate dielectric is formed over the supplemental gate dielectric, above the gap over the top surface of the body, and over at least a portion of the junction implants. The gate contact is formed over the primary gate dielectric.

Abstract: A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.