Patents by Inventor Andreas Meiser

Andreas Meiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190348525
    Abstract: The disclosure relates to a method for producing a semiconductor device. The method includes providing a semiconductor body having first dopants of a first conductivity type and second dopants of a second conductivity type. The method also includes forming a first trench in the semiconductor body via a first mask, and filling the first trench with a semiconductor filling material. The method further includes forming a superjunction structure by introducing a portion of the first dopants from a region of the semiconductor body into the semiconductor filling material, forming a second trench in the semiconductor body via a second mask, which is formed in a manner self-aligned with respect to the first mask, and forming a trench structure in the second trench.
    Type: Application
    Filed: May 10, 2019
    Publication date: November 14, 2019
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 10453915
    Abstract: A semiconductor device includes a semiconductor body having a semiconductor substrate of a first conductivity type and a semiconductor layer of the first conductivity type on the substrate. A trench structure extends into the semiconductor body from a first surface and includes a gate electrode and at least one field electrode arranged between the gate electrode and a bottom side of the trench structure. A body region adjoins the trench structure and laterally extends from a transistor cell area into an edge termination area. A pn junction is between the body region and semiconductor layer. A doping concentration of at least one of the body region and semiconductor layer is lowered at a lateral end of the pn junction in the edge termination area compared to a doping concentration of the at least one of the body region and semiconductor layer at the pn junction in the transistor cell area.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Karl-Heinz Bach, Christian Kampen, Dietmar Kotz, Andrew Christopher Graeme Wood, Markus Zundel
  • Publication number: 20190312114
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type on the semiconductor substrate, such that a first section of a pn junction is formed between the semiconductor layer and the semiconductor substrate. A trench structure extends through the semiconductor layer into the semiconductor substrate. The trench structure includes an insulation structure and a contact structure. The insulation structure is formed between the semiconductor layer and the contact structure. The contact structure is electrically connected to the semiconductor substrate at a bottom of the trench. A first semiconductor region of the second conductivity type adjoins the insulation structure and extends along the trench structure into a depth range between the first section of the pn junction and the bottom, such that a second section of the pn junction is formed between the first semiconductor region and the semiconductor substrate.
    Type: Application
    Filed: April 5, 2019
    Publication date: October 10, 2019
    Inventors: Andreas Meiser, Ralf Rudolf
  • Patent number: 10439030
    Abstract: A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Rolf Weis, Franz Hirler, Martin Vielemeyer, Markus Zundel, Peter Irsigler
  • Publication number: 20190296110
    Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a silicon carbide portion. A shielding region between a drift zone and the trench gate structures along a vertical direction orthogonal to the first surface forms an auxiliary pn junction with the drift zone. Channel regions and the trench gate structures are successively arranged along a first horizontal direction. The channel regions are arranged between a source region and a current spread region along a second horizontal direction orthogonal to the first horizontal direction. Portions of mesa sections between neighboring trench gate structures fully deplete at a gate voltage within an absolute maximum rating of the semiconductor device.
    Type: Application
    Filed: March 20, 2019
    Publication date: September 26, 2019
    Inventors: Andreas Meiser, Anton Mauder, Roland Rupp, Oana Julia Spulber
  • Publication number: 20190287804
    Abstract: A method includes: forming first and second trenches in a semiconductor body; forming a first material layer on the semiconductor body in the first and second trenches such that a first residual trench remains in the first trench and a second residual trench remains in the second trench; removing the first material from the second trench; and forming a second material layer on the first material layer in the first residual trench and on the semiconductor body in the second trench. The first material layer includes dopants of a first doping type and the second material layer includes dopants of a second doping type. The method further includes diffusing dopants from the first material layer in the first trench into the semiconductor body to form a first doped region, and from the second material layer in the second trench into the semiconductor body to form a second doped region.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 19, 2019
    Inventors: Rolf Weis, Thomas Gross, Hermann Gruber, Franz Hirler, Andreas Meiser, Markus Rochel, Till Schloesser, Detlef Weber
  • Publication number: 20190259870
    Abstract: A semiconductor device includes a trench structure extending from a first surface into a semiconductor body composed of silicon carbide. The trench structure includes an electrode and between the electrode and the first surface a gate electrode. A shielding region adjoining the electrode forms a first pn junction with a drift structure formed in the semiconductor body. A Schottky contact is formed between the drift structure and a first contact structure.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 22, 2019
    Inventor: Andreas Meiser
  • Patent number: 10381475
    Abstract: A semiconductor device and a method of manufacturing the same is provided. The semiconductor device including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: August 13, 2019
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Andreas Meiser, Karl-Heinz Gebhardt, Till Schloesser, Detlef Weber
  • Patent number: 10355087
    Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Martin Vielemeyer, Andreas Meiser, Till Schloesser, Franz Hirler, Martin Poelzl
  • Publication number: 20190198609
    Abstract: A transistor arrangement includes: a layer stack with first and second semiconductor layers of complementary first and second doping types; a first source region of a first transistor device adjoining the first semiconductor layers; a first drain region of the first transistor device adjoining the second semiconductor layers and spaced apart from the first source region; gate regions of the first transistor device, each gate region adjoining at least one second semiconductor layer, being arranged between the first source region and the first drain region, and being spaced apart from the first source region and the first drain region; a third semiconductor layer adjoining the layer stack and each of the first source region, first drain region, and each gate region; and active regions of a second transistor device integrated in the third semiconductor layer in a second region spaced apart from a first region of the third semiconductor layer.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Inventors: Rolf Weis, Henning Feick, Franz Hirler, Andreas Meiser
  • Publication number: 20190194587
    Abstract: This invention relates to a floating horizontal tubular photobioreactor system comprising a photosynthetically active area made of flexible tubes connected to rigid manifolds with an integrated system for mixing, aeration and degassing. This invention further relates to methods of using the floating photobioreactor system.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Inventors: Michael Welch, Lawrence Walmsley, Andreas Meiser, George Philippidis
  • Publication number: 20190189742
    Abstract: The disclosure relates to a semiconductor device including a first planar field effect transistor cell and a second planar field effect transistor cell. The first planar field effect transistor cell and the second planar field effect transistor cell are electrically connected in parallel and each include a drain extension region between a channel region and a drain terminal at a first surface of a semiconductor body. A gate electrode of the first field effect transistor cell is electrically connected to a source terminal, and a gate electrode of the second field effect transistor cell is connected to a gate terminal that is electrically isolated from the source terminal.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 20, 2019
    Inventors: Andreas Meiser, Christian Kampen
  • Publication number: 20190189743
    Abstract: The disclosure relates to a planar field effect transistor. The planar field effect transistor includes a drain extension region between a channel region and a drain terminal at a first surface of a semiconductor body. The planar field effect transistor also includes a first electrode part and a second electrode part laterally spaced apart from the first electrode part. The first electrode part is arranged as a gate electrode above the channel region. The second electrode part is arranged above the drain extension region and is electrically isolated from the first electrode part.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 20, 2019
    Inventors: Andreas Meiser, Grzegorz Kozlowski
  • Publication number: 20190157449
    Abstract: A semiconductor device includes a semiconductor body includes a first side and a second side opposite to the first side, a first dielectric disposed on the first side, a second dielectric disposed on the second side, one or more FET devices disposed at the first side, a first contact trench extending through the first dielectric at the first side, a first conductive material disposed in the first contact trench and electrically connected to the semiconductor body, a second contact trench extending through the second dielectric and into the semiconductor body at the second side, and a second conductive material disposed in the second contact trench and electrically connected to the semiconductor body at sidewalls of the second contact trench.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 23, 2019
    Inventors: Markus Zundel, Andreas Meiser, Hans-Peter Lang, Thorsten Meyer, Peter Irsigler
  • Patent number: 10277219
    Abstract: In accordance with an embodiment, an electronic circuit includes a first transistor device, at least one second transistor device, and a drive circuit. The first transistor device is integrated in a first semiconductor body, and includes a first load pad at a first surface of the first semiconductor body and a control pad and a second load pad at a second surface of the first semiconductor body. The at least one second transistor device is integrated in a second semiconductor body, and includes a first load pad at a first surface of the second semiconductor body and a control pad and a second load pad at a second surface of the second semiconductor body. The first load pad of the first transistor device and the first load pad of the at least one second transistor device are mounted to an electrically conducting carrier.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 30, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Rainald Sander, Andreas Meiser
  • Patent number: 10246325
    Abstract: A method for producing a MEMS device comprises forming a semiconductor layer stack, the semiconductor layer stack comprising at least a first monocrystalline semiconductor layer, a second monocrystalline semiconductor layer and a third monocrystalline semiconductor layer, the second monocrystalline semiconductor layer formed between the first and third monocrystalline semiconductor layers. A semiconductor material of the second monocrystalline semiconductor layer is different from semiconductor materials of the first and third monocrystalline semiconductor layers. After forming the semiconductor layer stack, at least a portion of each of the first and third monocrystalline semiconductor layers is concurrently etched.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 2, 2019
    Assignee: Infineon Technologies AG
    Inventors: Stefan Kolb, Andreas Meiser, Till Schloesser, Wolfgang Werner
  • Publication number: 20190097042
    Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a semiconductor body of silicon carbide. The trench gate structures include a gate electrode and are spaced apart from one another along a first horizontal direction and extend into a body region with a longitudinal axis parallel to the first horizontal direction. First sections of first pn junctions between the body regions and a drift structure are tilted to the first surface and parallel to the first horizontal direction. Source regions form second pn junctions with the body regions. A gate length of the gate electrode along a second horizontal direction orthogonal to the first horizontal direction is greater than a channel length between the first sections of the first pn junctions and the second pn junctions.
    Type: Application
    Filed: September 27, 2018
    Publication date: March 28, 2019
    Inventors: Andreas Meiser, Romain Esteve, Roland Rupp
  • Patent number: 10205019
    Abstract: One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part of the fin, a drain extension region of a first conductivity type, a source region and a drain region of the first conductivity type, a source contact in contact with the source region, and a gate structure adjoining opposing walls of the fin. The source contact extends along a vertical direction along the source region. The source contact includes a conductive material and is disposed in a trench in the semiconductor body, adjacent to the source region. The body region and the drain extension region are arranged one after another between the source region and the drain region.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Christian Kampen
  • Patent number: 10205016
    Abstract: A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser, Detlef Weber, Karl-Heinz Gebhardt
  • Patent number: 10170615
    Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type. The source region and the drain region are arranged in a first direction parallel to a first main surface of a semiconductor substrate. The semiconductor device further includes a layer stack having a drift layer of the first conductivity type and a compensation layer of a second conductivity type. The drain region is electrically connected with the drift layer. The semiconductor device also includes a connection region of the second conductivity type extending into the semiconductor substrate, the connection region being electrically connected with the compensation layer, wherein the buried semiconductor portion does not fully overlap with the drift layer.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 1, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Andreas Meiser, Till Schloesser