Patents by Inventor Andreas Meiser

Andreas Meiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9748378
    Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The gate electrode is disposed in trenches extending in a first direction parallel to the first main surface. The gate electrode is electrically coupled to a gate terminal. The channel region and the drift zone are disposed along the first direction between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode. The conductive layer is electrically connected to the gate terminal.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: August 29, 2017
    Assignee: Infineon Technologies AG
    Inventors: Karoline Koepp, Andreas Meiser, Till Schloesser
  • Publication number: 20170236931
    Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a source contact, the source contact including a first and second source contact portion, and a gate electrode in a gate trench in the first main surface adjacent to a body region. The body region and a drift zone are disposed along a first direction parallel to the first main surface between the source region and a drain region. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region, the first source contact portion further including a portion of the semiconductor substrate between the source conductive material and the second source contact portion. The semiconductor device further includes a temperature sensor in the semiconductor substrate.
    Type: Application
    Filed: February 10, 2017
    Publication date: August 17, 2017
    Applicant: Infineon Technologies AG
    Inventors: Andreas MEISER, Till SCHLOESSER
  • Patent number: 9735243
    Abstract: A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: August 15, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Rolf Weis, Franz Hirler, Martin Vielemeyer, Markus Zundel, Peter Irsigler
  • Patent number: 9728580
    Abstract: A power transistor has a semiconductor body with a bottom side and top side spaced distant from the bottom side in a vertical direction. The semiconductor body includes a plurality of transistor cells, a source zone of a first conduction type, a body zone of a second conduction type, a drift zone of the first conduction type, a drain zone, and a temperature sensor diode having a pn-junction between an n-doped cathode zone and a p-doped anode zone. The power transistor also has a drain contact terminal on the top side, a source contact terminal on the bottom side, a gate contact terminal, and a temperature sense contact terminal on the top side. Depending on the first and second conduction types the anode or cathode zone is electrically connected to the source contact terminal and the other diode zone is electrically connected to the temperature sense contact terminal.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Steffen Thiele
  • Publication number: 20170222043
    Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type. The source region and the drain region are arranged in a first direction parallel to a first main surface of a semiconductor substrate. The semiconductor device further includes a layer stack having a drift layer of the first conductivity type and a compensation layer of a second conductivity type. The drain region is electrically connected with the drift layer. The semiconductor device also includes a connection region of the second conductivity type extending into the semiconductor substrate, the connection region being electrically connected with the compensation layer, wherein the buried semiconductor portion does not fully overlap with the drift layer.
    Type: Application
    Filed: January 26, 2017
    Publication date: August 3, 2017
    Inventors: Franz Hirler, Anton Mauder, Andreas Meiser, Till Schloesser
  • Publication number: 20170213783
    Abstract: A semiconductor package is disclosed. The semiconductor package includes an electrically conducting carrier having a mounting surface, a first level first semiconductor power device having a first load electrode mounted over the mounting surface of the electrically conducting carrier and having a second load electrode opposite the first electrode. The package further includes a first level second semiconductor power device. A first connection element has a first surface connected to the second load electrode of the first level first semiconductor power device. A second connection element has a first surface connected to the second load electrode of the first level second semiconductor power device. The package includes a second level first semiconductor power device and a second level second semiconductor power device.
    Type: Application
    Filed: January 25, 2017
    Publication date: July 27, 2017
    Applicant: Infineon Technologies AG
    Inventors: Andreas Meiser, Matthias Grewe, Stefan Macheiner
  • Patent number: 9705026
    Abstract: A method of triggering avalanche breakdown in a semiconductor device includes providing an electrical coupling and an optical coupling between an auxiliary semiconductor device configured to emit radiation and the semiconductor device including a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer. The electrical and optical coupling includes triggering emission of radiation by the auxiliary semiconductor device and triggering avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: July 11, 2017
    Assignee: Infineon Technologies AG
    Inventors: Joost Willemen, Michael Mayerhofer, Ulrich Glaser, Yiqun Cao, Andreas Meiser, Magnus-Maria Hell, Matthias Stecher, Julien Lebon
  • Publication number: 20170162660
    Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.
    Type: Application
    Filed: February 21, 2017
    Publication date: June 8, 2017
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 9673320
    Abstract: A transistor cell includes a drift region, a source region, a body region, and a drain region that is laterally spaced apart from the source region. A gate electrode is adjacent the body region. A field electrode is arranged in the drift region. A source electrode is connected to the source region and the body region, and a drain electrode is connected to the drain region. An avalanche bypass structure is coupled between the source electrode and the drain electrode and includes a first semiconductor layer of the first doping type, a second semiconductor layer of the first doping type, and a pn-junction arranged between the first semiconductor layer and the source electrode. The second semiconductor layer has a higher doping concentration than the first semiconductor layer and is arranged between the second semiconductor layer and the drift region. The drain electrode is electrically connected to the second semiconductor layer.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: June 6, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 9661707
    Abstract: A semiconductor device includes first and second field effect transistors (FETs) formed in a semiconductor substrate having a first main surface. The first FET includes first source and drain contact grooves, each running in a first direction parallel to the first main surface, each formed in the first main surface. First source regions are electrically connected to a conductive material in the first source contact groove. First drain regions are electrically connected to a conductive material in the first drain contact groove. The second FET includes second source and drain contact grooves, each running in a second direction parallel to the first main surface, each formed in the first main surface. Second source regions are electrically connected to a conductive material in the second source contact groove, and second drain regions are electrically connected to a conductive material in the second drain contact groove.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 9660055
    Abstract: A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Till Schloesser, Andreas Meiser
  • Publication number: 20170141105
    Abstract: A semiconductor device includes a first transistor and a second transistor in a semiconductor substrate. The first transistor includes a first drain contact electrically connected to a first drain region, the first drain contact including a first drain contact portion and a second drain contact portion. The first drain contact portion includes a drain conductive material in direct contact with the first drain region. The second transistor includes a second source contact electrically connected to a second source region. The second source contact includes a first source contact portion and a second source contact portion. The first source contact portion includes a source conductive material in direct contact with the second source region.
    Type: Application
    Filed: November 15, 2016
    Publication date: May 18, 2017
    Applicant: Infineon Technologies AG
    Inventors: Andreas MEISER, Dirk AHLERS, Till SCHLOESSER
  • Publication number: 20170117383
    Abstract: A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate. Additionally, the method includes connecting a carrier substrate to the oxide layer and processing a back side of the semiconductor substrate.
    Type: Application
    Filed: January 5, 2017
    Publication date: April 27, 2017
    Inventors: Andreas Meiser, Anton Mauder, Markus Zundel, Hans-Joachim Schulze, Franz Hirler, Hans Weber
  • Patent number: 9634101
    Abstract: A MOS transistor semiconductor component includes a semiconductor body with first and second surfaces, a first contact electrode on the first surface, a second contact electrode on the second surface, a first insulation layer separating a via region at least from a drift region, a monocrystalline semiconductor region arranged in the via region and extending between the first surface and the second surface, a gate electrode electrically connected to the first contact electrode, a source electrode electrically insulated from the gate electrode, and arranged at least partially above the first surface, and a drain electrode electrically insulated from the second contact electrode on the second surface. The MOS transistor has a gate terminal formed by the second contact electrode and electrically connected to a gate-electrode of the MOS transistor through the via region. The gate-electrode is formed next to the first surface and disposed outside the via region.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: April 25, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Andreas Meiser
  • Patent number: 9620637
    Abstract: A semiconductor device formed in a semiconductor substrate includes a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region. The gate electrode is disposed adjacent at least two sides of the body region, and the source region and the gate electrode are coupled to a source terminal. A width of the body region between the two sides of the body region is selected so that the body region is configured to be fully depleted.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser, Franz Hirler
  • Patent number: 9614032
    Abstract: A semiconductor device comprises a transistor in a semiconductor body having a first main surface and a second main surface, the first main surface being opposite to the second main surface. The transistor comprises a source region at the first main surface, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The gate electrode is disposed in trenches extending in the first direction. The transistor further comprises an insulating layer adjacent to the second main surface of the body region. The source region vertically extends to the second main surface.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: April 4, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 9614064
    Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a body region, and a gate electrode structure adjacent to the body region. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. The body region is disposed between the source region and the drain region. The body region includes an upper body region at the main surface and a lower body region remote from the main surface. A first width of the lower body region is smaller than a second width of the upper body region. The first width and the second width are measured in a direction perpendicular to the first direction.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 4, 2017
    Assignee: Infineon Technologies AG
    Inventor: Andreas Meiser
  • Publication number: 20170092717
    Abstract: A trench etch mask is formed on a process surface of a semiconductor layer. By using the trench etch mask, both first trenches and second trenches are formed that extend from the process surface into the semiconductor layer. The first and second trenches alternate along at least one horizontal direction parallel to the process surface. First semiconductor regions of a first conductivity type are formed in the first trenches. Second semiconductor regions of a second, opposite conductivity type are formed in the second trenches.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 30, 2017
    Inventors: Andreas Meiser, Franz Hirler
  • Patent number: 9608070
    Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Publication number: 20170084606
    Abstract: An integrated circuit includes a semiconductor body with a first semiconductor layer, an insulation layer on the first semiconductor layer, and a second semiconductor layer on the insulation layer. The integrated circuit further includes a plurality of transistors each including a load path and a control node The load paths are connected in series, and the plurality of transistors are at least partially integrated in the second semiconductor layer. A voltage limiting structure is connected in parallel with the load path of one of the plurality of transistors, wherein the voltage limiting structure is integrated in the first semiconductor layer and is connected to the one of the plurality of transistors through two electrically conducting vias extending through the insulation layer.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 23, 2017
    Inventors: Andreas Meiser, Dirk Priefert, Rolf Weis