Patents by Inventor Andreas Meiser

Andreas Meiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9953968
    Abstract: An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a second terminal and being operable at voltage differences between the first terminal and second terminal of greater than +10 V and less than ?10 V. The integrated circuit additionally includes an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal. The ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than ?10 V without triggering. The ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: April 24, 2018
    Assignee: Infineon Technologies AG
    Inventors: Yiqun Cao, Ulrich Glaser, Magnus-Maria Hell, Julien Lebon, Michael Mayerhofer, Andreas Meiser, Matthias Stecher, Joost Willemen
  • Publication number: 20180108675
    Abstract: In accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity. The integrated circuit further includes a trench isolation structure configured to provide a lateral electric isolation of the active area portion.
    Type: Application
    Filed: October 17, 2017
    Publication date: April 19, 2018
    Inventors: Sebastian Schmidt, Donald Dibra, Oliver Hellmund, Peter Irsigler, Andreas Meiser, Hans-Joachim Schulze, Martina Seider-Schmidt, Robert Wiesner
  • Patent number: 9947648
    Abstract: A semiconductor device includes a semiconductor body including a first trench extending into the semiconductor body from a first surface and a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench. The other one of the anode region and the cathode region includes a first semiconductor region directly adjoining the one of the anode region and the cathode region from outside of the first trench, thereby constituting a pn junction. The semiconductor device further includes a conducting path through a sidewall of the first trench.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: April 17, 2018
    Assignee: Infineon Technologies AG
    Inventors: Joachim Weyers, Anton Mauder, Franz Hirler, Andreas Meiser, Ulrich Glaser
  • Patent number: 9941349
    Abstract: A trench etch mask is formed on a process surface of a semiconductor layer. By using the trench etch mask, both first trenches and second trenches are formed that extend from the process surface into the semiconductor layer. The first and second trenches alternate along at least one horizontal direction parallel to the process surface. First semiconductor regions of a first conductivity type are formed in the first trenches. Second semiconductor regions of a second, opposite conductivity type are formed in the second trenches.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 10, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Franz Hirler
  • Publication number: 20180097074
    Abstract: A method of manufacturing a semiconductor device is providing, which includes forming a trench in a semiconductor substrate, forming an oxide layer over sidewalls and over a bottom side of the trench, performing an ion implantation process, forming a cover layer, and patterning the covering layer, thereby forming an uncovered area and a covered area of the oxide layer, respectively. The method further includes performing an isotropic etching process thereby removing portions of the uncovered area of the oxide layer and removing a part of a surface portion of the covered area adjacent to the uncovered portions, and removing remaining portions of the covering layer.
    Type: Application
    Filed: December 6, 2017
    Publication date: April 5, 2018
    Applicant: Infineon Technologies AG
    Inventors: Andreas Meiser, Oliver Haeberlen
  • Patent number: 9935055
    Abstract: A method of manufacturing a semiconductor device includes forming a separation trench into a first main surface of a semiconductor substrate and removing substrate material from a second main surface of the semiconductor substrate, so as to thin the substrate to a thickness of less than 100 ?m, the second main surface being opposite to the first main surface, so as to uncover a bottom side of the trench. Additional methods of manufacturing semiconductor devices are provided.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: April 3, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
  • Patent number: 9917163
    Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 9911686
    Abstract: A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: March 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Andreas Meiser, Martin Mischitz, Michael Roesner, Michael Pinczolits
  • Patent number: 9893158
    Abstract: A semiconductor device is provided that includes a transistor in a semiconductor body having a main surface. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region. The first direction is parallel to the main surface. The semiconductor device further includes a field plate disposed in field plate trenches extending along the first direction in the drift zone, and a field dielectric layer between the field plate and the drift zone. A thickness of the field dielectric layer gradually increases along the first direction from a portion adjacent to the source region to a portion adjacent to the drain region.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: February 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Oliver Haeberlen
  • Patent number: 9893178
    Abstract: A semiconductor device includes a transistor formed in a semiconductor substrate having a main surface. The transistor includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, a gate trench adjacent to a first sidewall of the channel region, a gate conductive material disposed in the gate trench, the gate conductive material being connected to a gate terminal, and a channel separation trench adjacent to a second sidewall of the channel region. The second sidewall faces the first sidewall via the channel region. The channel separation trench is filled with an insulating separation trench filling consisting of an insulating material in direct contact with the channel region. The source region and the drain region are disposed along a first direction. The first direction is parallel to the main surface.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: February 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser, Franz Hirler
  • Publication number: 20180040729
    Abstract: A semiconductor device and a method of manufacturing the same is provided. The semiconductor device including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.
    Type: Application
    Filed: October 17, 2017
    Publication date: February 8, 2018
    Applicant: Infineon Technologies Dresden GmbH
    Inventors: Andreas MEISER, Karl-Heinz GEBHARDT, Till SCHLOESSER, Detlef WEBER
  • Patent number: 9882555
    Abstract: A switch is provided having a switch transistor as well as a monitoring component to monitor a control signal applied to the switch transistor. With the monitoring component, in some implementation a monitoring of the control signal independent from a load path may be possible.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: January 30, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Anton Mauder, Jens Barrenscheen
  • Publication number: 20180006639
    Abstract: In accordance with an embodiment, an electronic circuit includes a first transistor device, at least one second transistor device, and a drive circuit. The first transistor device is integrated in a first semiconductor body, and includes a first load pad at a first surface of the first semiconductor body and a control pad and a second load pad at a second surface of the first semiconductor body. The at least one second transistor device is integrated in a second semiconductor body, and includes a first load pad at a first surface of the second semiconductor body and a control pad and a second load pad at a second surface of the second semiconductor body. The first load pad of the first transistor device and the first load pad of the at least one second transistor device are mounted to an electrically conducting carrier.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 4, 2018
    Inventors: Rainald Sander, Andreas Meiser
  • Patent number: 9859418
    Abstract: A semiconductor device is provided including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Andreas Meiser, Karl-Heinz Gebhardt, Till Schloesser, Detlef Weber
  • Publication number: 20170373678
    Abstract: A switch is provided having a switch transistor as well as a monitoring component to monitor a control signal applied to the switch transistor. With the monitoring component, in some implementation a monitoring of the control signal independent from a load path may be possible.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Andreas Meiser, Anton Mauder, Jens Barrenscheen
  • Publication number: 20170373685
    Abstract: Switch devices using switch transistors with dual gates are provided. The dual gates may be controlled independently from each other by first and second gate driver circuits.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Andreas Meiser, Anton Mauder, Jens Barrenscheen
  • Patent number: 9852945
    Abstract: A semiconductor device is manufactured at least partially in a semiconductor substrate. The substrate has first and second opposing main surfaces. The method includes forming a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, and forming the cell field portion by at least forming a transistor. The method further includes insulating a part of the semiconductor substrate from other substrate portions to form a connection substrate portion, forming an electrode adjacent to the second main surface so as to be in contact with the connection substrate portion, forming an insulating layer over the first main surface, forming a metal layer over the insulating layer, forming a trench in the first main surface, and filling the trench with a conductive material, and electrically coupling the connection substrate portion to the metal layer via the trench.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Till Schloesser, Martin Poelzl
  • Patent number: 9853637
    Abstract: Switch devices using switch transistors with dual gates are provided. The dual gates may be controlled independently from each other by first and second gate driver circuits.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Anton Mauder, Jens Barrenscheen
  • Publication number: 20170358650
    Abstract: A semiconductor device includes a transistor in a semiconductor substrate. The transistor includes a drift zone of a first conductivity type adjacent to a drain region, and a first field plate and a second field plate adjacent to the drift zone. The second field plate is arranged between the first field plate and the drain region. The second field plate is electrically connected to a contact portion arranged in the drift zone. The transistor further includes an intermediate portion of the first conductivity type at a lower doping concentration than the drift zone. A distance between the intermediate portion and the drain region is smaller than the distance between the contact portion and the drain region.
    Type: Application
    Filed: June 6, 2017
    Publication date: December 14, 2017
    Inventors: Andreas Meiser, Franz Hirler, Till Schloesser
  • Patent number: 9825170
    Abstract: A semiconductor device formed in a semiconductor substrate having a first main surface comprises a transistor array and a termination region. The transistor array comprises a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region. The gate electrode is disposed in first trenches. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a first ridge extending along the first direction. The termination region comprises a termination trench, a portion of the termination trench extending in the first direction, a length of the termination trench being larger than a length of the first trenches, the length being measured along the first direction.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: November 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Franz Hirler, Andreas Meiser, Till Schloesser