Abstract: Some embodiments of the invention provide a method of specifying a cost function that represents the estimated distance between an external state and a set of states in a multi-state space that represents a region of a design layout. The method identifies a first polygon that encloses the set of states. It then identifies vectors to project from the vertices of the first polygon. Based on the projected vectors, the method specifies a first cost function. The method also identifies a second polygon that encloses the set of states. It also identifies vectors to project from the vertices of the second polygon. Based on the projected vectors, the method specifies a second cost function. The method then derives a third cost function from the specified cost functions.

Abstract: Some embodiments provide a method of computing the estimated distance between an external state and a set of states in a multi-state space that represents a region of a design layout. The method identifies a polygon that encloses the set of states. It then identifies vectors to project from the vertices of the polygon based on a model that allows penalizes measurements in certain directions more than other directions. Based on the projected vectors, the method then identifies the estimated distance.

Abstract: Some embodiments of the invention provide a method of specifying a cost function that represents the estimated distance between an external state and a set of states in a multi-state space that represents a region of a design layout. The method identifies a polygon that encloses the set of states. It then identifies vectors to project from the vertices of the polygon. Based on the projected vectors, the method identifies a set of distances that includes the distance between the polygon and each point in a set of points in the external state. The method then uses the identified set of distance to specify the cost function.

Abstract: Some embodiments of the invention provide an integrated-circuit chip that has a design based on a wiring model that allows at least a particular wiring layer to have more than one preferred wiring directions. Other embodiments provide a method of manufacturing an integrated circuit (“IC”) that has a plurality of wiring layers. The method specifies a layout of the IC by using a wiring model that specifies more than one preferred wiring direction for at least a region of a particular wiring layer. The method then uses the layout to fabricate the integrated circuit.

Abstract: Some embodiments of the invention provide a method of decomposing a region of an intergrated circuit (“IC”) layout. The region contains several routable elements. Based on the routable elements, the method defines a plurality of nodes in the region. It then triangulates the region based on the nodes. The method then uses the triangles to define routes in the region.

Abstract: Some embodiments of the invention provide a method of decomposing a region of an intergrated circuit (“IC”) layout. The method defines several nodes in the region. The method then specifies a plurality of edges in the region. Each edge is between a pair of nodes, and some edges are neither perpendicular nor parallel to some of the edges. The method uses the edges to define routes in the region.

Abstract: Some embodiments of the invention provide a method of expanding a path in a space with dimensional states. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. The method identifies a first expansion for the path from a start state to a first destination state. It then specifies a first cost function that expresses the cost of the first expansion. The first cost function is defined over the destination state. The method also identifies a second expansion for the path from a first portion of the first destination state to a second destination state. From a portion of the first cost function that is defined over the first portion of the first destination state, the method computes a second cost function that specifies the cost of the second expansion.

Abstract: Some embodiments of the invention provide a method of routing nets in a region of a layout with multiple layers. The method defines a routing graph that has several of nodes on plurality of layers, where each node represents a sub-region on a layer. In the graph, there is a set of edges between the nodes on each layer. On one layer, there is at least one set of edges that are neither orthogonal nor parallel to a set of edges on another layer. The method uses this routing graph to identify routes.

Abstract: Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a surface. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method projects vectors from points on the first state that are locations of inflection points in the first PLF. At each intersection of the boundary of the surface and one of the vectors, the method computes a cost. Based on the computed costs, the method specifying a second PLF that is defined over the second state.

Abstract: Some embodiments of the invention provide a method of defining a global route for a net in a region of a layout, where each net has a set of routable elements. The method partitions the region into several rectangular sub-regions. It then identifies a set of sub-regions that contain the routable elements of the net. Next, it defines a global route that connects the identified sub-regions, where the global route includes at least one non-Manhattan edge that crosses a boundary between two sub-regions at a non-vertex location.

Abstract: Some embodiments provide a path-searching method. This method identifies two sets of states in a multi-state space, where at least some of the states have at least one dimension. The method performs a depth-first path search to identify a path between the two sets of states. During the path search, the method propagates a cost function that is defined over one state to another state.

Abstract: Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a point. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method projects vectors from points on the first state that are locations of inflection points in the first PLF. If the second state is between two projected vectors that emanate from a vector-emanating point on the first state, the method then computes a cost at the second state that equals the sum of the cost of the first PLF at the vector-emanating point and the distance between the vector-emanating point and the second state in the design layout.

Abstract: Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ.

Abstract: Some embodiments of the invention provide a region of an integrated-circuit (“IC”) layout that has a plurality of interconnect layers, where at least one particular layer has more than one preferred interconnect direction. In some of these embodiments, the region has several interconnect layers that have more than one preferred wiring direction each.

Abstract: Some embodiments provide an integrated circuit that includes several circuits. The integrated circuit further includes a first interconnect wiring layer that has a first preferred direction of interconnect wiring. The integrated circuit also includes a second interconnect wiring layer that has a second preferred direction of interconnect wiring, where the first and second preferred directions of interconnect wiring are neither orthogonal nor parallel. The integrated circuit also includes several interconnect wiring on the first and second interconnect wiring layers that couples the circuits and are not aligned with any grid other than a manufacturing grid.

Abstract: Some embodiments of the invention provide a method of for routing nets within a region of an integrated circuit (“IC”) layout. The method selects a net in the IC layout region. It then identifies a topological route for the selected net. From the selected net's topological route, this method then generates a geometric route for the selected net.

Abstract: Some embodiments of the invention provide a method for identifying topological routes in a region of an integrated circuit (“IC”) design layout. The method receives a set of nets. Each net in the set has a set of routable elements in the IC design-layout region. For each net, the method then specifies a topological route that connects the net's routable elements. Each topological route is a route that represents a set of diffeomorphic geometric routes.

Abstract: Some embodiments of the invention provide a method of routing nets in a region of an integrated-circuit (“IC”) layout. The method selects a net that has several routable elements. It then defines a route for the net. To define the route, the method uses a wiring model that specifies preferred non-Manhattan wiring directions. It also uses a manufacturing grid as the only grid for constraining the location of interconnect lines for connecting the net's routable elements.

Abstract: One embodiment of the invention is a method of routing a group of nets in a region. The method identifies a first route for a first net. It then determines whether embedding the first route in the region will make a set of unrouted nets in the region unroutable. When embedding the first route will make the set of unrouted nets unroutable, the method then identifies a second route for the first net. If embedding a route will not make the set of unrouted nets unroutable, the method embeds the route in the region.

Abstract: Some embodiments of the invention provide a method of identifying routes in a region of an integrated circuit (“IC”) design layout. The region contains at least one net with several routable elements. The method decomposes the IC design-layout region into a tessellated graph. The tessellated graph includes a plurality of edges. The method then specifies a route that connects the net's routable elements by specifying a set of edges that the route intersects.