Patents by Inventor Andrew Caldwell

Andrew Caldwell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7535252
    Abstract: Some embodiments provide a method of operating a configurable circuit. The method performs a first operation by the configurable circuit based on a first configuration data set. When a user-design signal has a value from a set of values, the method performs a second operation based on a second configuration data set, after the first operation. When the user-design signal does not have a value from said set of values, the method performs a third operation based on a third configuration data set, after the first operation. Some embodiments provide a reconfigurable IC that includes a set of reconfigurable circuits and sets of associated configuration storage elements that store configuration data sets. At least one reconfigurable circuit receives a first sub-set of its configuration data when a user-design signal has a first value and receives a second sub-set of its configuration data when the user-design signal has a second value.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: May 19, 2009
    Assignee: Tabula, Inc.
    Inventors: Steven Teig, Andrew Caldwell, Jason Redgrave
  • Patent number: 7530033
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: May 5, 2009
    Assignee: Tabula, Inc.
    Inventors: Andrew Caldwell, Herman Schmit, Steven Teig
  • Publication number: 20090077522
    Abstract: Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a route for the net based on different congestion goals on different layers. In other embodiments, the method identifies a route for the net based on different congestion goals between different layer pairs. In some embodiments, the method identifies a route for the net based on both the different congestion goals on different layers and between different layer pairs.
    Type: Application
    Filed: December 1, 2008
    Publication date: March 19, 2009
    Inventors: Jonathan Frankle, Andrew Caldwell
  • Patent number: 7480885
    Abstract: Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a route for the net based on different congestion goals on different layers. In other embodiments, the method identifies a route for the net based on different congestion goals between different layer pairs. In some embodiments, the method identifies a route for the net based on both the different congestion goals on different layers and between different layer pairs.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: January 20, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jonathan Frankle, Andrew Caldwell
  • Publication number: 20090007027
    Abstract: Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit elements(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 1, 2009
    Inventors: Brad Hutchings, Andrew Caldwell, Steven Teig
  • Patent number: 7461362
    Abstract: Some embodiments provided a method of designing a configurable IC. The method includes receiving a first design that has at least one controllable circuit that is initialized by a first type of initialization signal. This first design also at least one controllable circuit that is initialized by a second type of initialization signal. The method defines a second design based on the first design. The method defines this second design by replacing all controllable circuits that are initialized by the first type of initialization signal with functionally equivalent controllable circuits. Each of these functionally equivalent controllable circuits includes a particular controllable circuit that is initialized by the second type initialization signal.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: December 2, 2008
    Assignee: Tabula, Inc.
    Inventors: Andrew Caldwell, Jason Redgrave
  • Patent number: 7372297
    Abstract: Some embodiments provide a reconfigurable IC that implements a design that is designed at a particular design clock rate. The reconfigurable IC includes reconfigurable circuits for performing operations on a set of inputs in the particular design. The IC further includes routing circuits for routing signals to and from the logic circuits to allow the logic circuits to perform the operations. The reconfigurable IC implements the design by having reconfigurable circuits that reconfigure at a rate faster than the design clock rate. For at least one operation which is defined at the design clock rate, the reconfigurable IC replicates the operation set in at least two reconfiguration cycles to reduce consumption of routing circuits.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: May 13, 2008
    Assignee: Tabula Inc.
    Inventors: Daniel J. Pugh, Andrew Caldwell
  • Patent number: 7310793
    Abstract: Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: December 18, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Publication number: 20070257700
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.
    Type: Application
    Filed: November 7, 2005
    Publication date: November 8, 2007
    Inventors: Andrew Caldwell, Herman Schmit, Steven Teig
  • Patent number: 7246338
    Abstract: Some embodiments of the invention provide a method for costing an expansion to a two-dimensional state in a path search that searches for a path between two sets of states in a space. The method identifies a cost function that is defined over the two-dimensional state. The method computes a second cost function that is defined over the two-dimensional state. It also computes a third cost function that is defined over the two-dimensional state. It then adds the second and third cost functions to obtain the first cost function.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: July 17, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 7236009
    Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: June 26, 2007
    Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
  • Patent number: 7155697
    Abstract: A method for routing of some embodiments defines global routes for nets in an arbitrary region of a circuit layout in which each net has a set of pins. The method uses a first set of lines of measure the length of the global routes, a second set of lines to measure congestion of the global routes, and a third set of lines to partition the arbitrary region into a first set of sub-regions. For each net, the method identifies a global route that connects a group of first-set sub-regions that contain the net's set of pins.
    Type: Grant
    Filed: January 13, 2002
    Date of Patent: December 26, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset, Etienne Jacques, Andrew Caldwell, Jonathan Frankle
  • Patent number: 7143383
    Abstract: The present invention introduces a method for implementing a gridless non Manhattan router by modifying an existing gridless Manhattan router. In the method of the present invention, a tile based router that uses tiles to represent circuit geometry or free space between circuit geometry is first selected. Next, at least one tile routing layer of the tile based router is rotated to implement a diagonal wiring layer. The code of the router is then adjusted to ensure that a via that will connect a Manhattan layer to a non Manhattan layer (a diagonal layer) will fit within a tile on both layers.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: November 28, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 7114141
    Abstract: Some embodiments of the invention provide a method of decomposing a design layout. The method decomposes the layout into a tessellated graph with several edges. It then computes the capacity of the edges based on a interconnect line model that is used to connect elements in the design layout. The layout has two orthogonal coordinate axes. At least one interconnect line specified by the model is neither parallel nor perpendicular to the coordinate axes. Also, in some embodiments, some of the edges are neither parallel nor perpendicular to the coordinate axes.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: September 26, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 7107564
    Abstract: One embodiment of the invention is a method of specifying routes for a group of nets. The method identifies different routing solutions for the group of nets. It then selects the best routing solution.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: September 12, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 7089524
    Abstract: Some embodiments of the invention provide a method for generating multi-layer topological routes in a region of a design layout. The method selects a net that has routable elements on a several interconnect layers. For the selected net, the method defines a topological route that connects the selected net's routable elements. The topological route includes a topological via that specifies the defined route's traversal from one interconnect layer to another interconnect layer, without having a coordinate within the region.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: August 8, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 7080329
    Abstract: Some embodiments of the invention provide a method of identifying a via between at least two layers of a multi-layer design layout. The method identifies a region within which the via should be located. It then formulates an optimization problem for identifying a location of the via in the region. It then solves the optimization problem to find an optimized location for the via.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: July 18, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 7073151
    Abstract: Some embodiments of the invention provide a method for identifying a path in a design layout. Based on the design layout, the method defines a triangulated graph that has sets of source and target states and two orthogonal axes. The method specifies at least one path that starts from one state. It then iteratively specifies new paths by expanding previously specified paths in the graph until identifying a path that connects the source and target states. At least one of the expansions of a previously specified path is an expansion to a line that is not aligned with the axes of the graph.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: July 4, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 7069530
    Abstract: One embodiment of the invention is a method of identifying a set of paths between a set of source routable elements of a net and a set of target routable elements of the net. The set of paths has to have a minimum acceptable number of paths. The method specifies a first total cost. It then performs a first depth-first search to identify the set of paths, where each path has a cost that does not exceed the first total cost, and each path includes a set of expansions from the set of routable-element sources to the set of routable-element targets. If the search cannot find the acceptable number of paths, it increments the total cost and performs a second depth-first search to identify the set of paths, where each path has a cost that does not exceed the incremented total cost.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: June 27, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 7069531
    Abstract: Some embodiments of the invention provide a method for identifying a path between a set of source states and a set of target states in a space with more than two dimensions. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. At least some of the states are non-zero dimensional states. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method specifies at least one path that starts from one state. It then iteratively specifies new paths by expanding previously specified paths to other states in the space until identifying a path that connects the source and target states. At least one of the expansions of a previously specified path includes an expansion in more than two dimensions of the space.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: June 27, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell