Abstract: Some embodiments of the invention provide a method of routing nets in a region of a layout with multiple layers. The method defines a routing graph that has several of nodes on plurality of layers, where each node represents a sub-region on a layer. In the graph, there is a set of edges between the nodes on each layer. On one layer, there is at least one set of edges that are neither orthogonal nor parallel to a set of edges on another layer. The method uses this routing graph to identify routes.

Abstract: Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a route for the net based on different congestion goals on different layers. In other embodiments, the method identifies a route for the net based on different congestion goals between different layer pairs. In some embodiments, the method identifies a route for the net based on both the different congestion goals on different layers and between different layer pairs.

Abstract: Some embodiments of the invention provide a method of defining a global route for a net in a region of a layout, where each net has a set of routable elements. The method partitions the region into several rectangular sub-regions. It then identifies a set of sub-regions that contain the routable elements of the net. Next, it defines a global route that connects the identified sub-regions, where the global route includes at least one non-Manhattan edge that crosses a boundary between two sub-regions at a non-vertex location.

Abstract: The present invention introduces several methods for implementing integrated circuits that use gridless non Manhattan routing to connect the integrated circuit components. In one embodiment, the non Manhattan routed integrated circuits are created by creating an initial route and then compacting the design down. In another embodiment, a gridless non Manhattan integrated circuits are implemented by adapting a gridless Manhattan routing system into a gridless non Manhattan routing system by rotating a plane of a tile based maze router.

Abstract: Some embodiments of the invention provide a method for defining routes for nets in a region of a circuit layout. This method uses a first set of lines to measure length of routes, and uses a second set of lines to measure congestion of routes.

Abstract: The present invention introduces methods for implementing gridless non Manhattan architecture for integrated circuits. In one particular embodiment, an integrated circuit layout containing horizontal, vertical, and diagonal interconnect lines is first created. Next, the integrated circuit layout is then compacted. The compacting method first creates groups of horizontal and diagonal interconnect lines sorted by vertical position and groups of vertical and diagonal interconnect lines sorted by horizontal position. The two groups are then compacted in a manner that ensures that a minimum manufacturing line spacing requirement is satisfied.