Abstract: Some embodiments of the invention provide a method of propagating a first cost function that is defined over a first state to a second slate in a space representing a design-layout region. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. The space has several dimensional states. The method identifies several pairs of wedge vectors. Each vector has a tail, and each wedge-vector pair includes two vectors that are connected at their tails. The method assigns locations in the first state for the tails of at least some of the identified wedge-vector pairs. The method then uses the wedge-vector pairs that have assigned tail locations to propagate the first cost function.

Abstract: Some embodiments of the invention provide a method of routing nets in an integrated-circuit layout region that has multiple interconnect layers. The method specifies several routes, where some of the routes utilize vias to traverse multiple interconnect layers. The method assesses a cost of at least one via proportionately to a cost that the via introduces in the design of the integrated circuit.

Abstract: Some embodiments of the invention provide a method of routing nets in a region of a design layout. The region contains a plurality of nets and has multiple interconnect layers. The method identifies routes for a set of nets in the region, where some of the routes utilize vias to traverse multiple interconnect layers. The method then moves at least one via to improve the routing.

Abstract: For a path search that identifies a path between source and target states in a space, some embodiments of the invention provide a method for determining viability of an expansion of a path from a first state to a second dimensional state. The method computes a first cost function that expresses the cost of the path to reach the second state. The first cost function is defined over the second state. The method then determines whether the first cost function expresses a better cost over any portion of the second state than a second cost function that expresses the best cost of paths that have reached the second state during the path search. The expansion is a viable one if the first cost function expresses a better cost over at least a portion of the second state than the second cost function.

Abstract: Some embodiments of the invention provide a path-searching method. This method identifies two sets of states in a multi-state space, where at least some of the states have at least one dimension. It then performs an epsilon-optimal path search to identify an epsilon-optimal path between the two set of states. The epsilon-optimal path is a path that is within an epsilon of the optimal path between the two sets of states. During the espsilon optimal search, the method propagates a cost function that is defined over one state to another state.

Abstract: Some embodiments of the invention provide an integrated circuit (“IC”) design layout that includes topological routes. This layout includes several nets, each with a set of routable elements in the IC design-layout region. For each net, this layout also includes a topological route that connects the net's routable elements. Each topological route is a route that represents a set of diffeomorphic geometric routes. In some embodiments, the IC layout further includes a topological graph that represents the IC design layout topologically. The topological graph includes several topological items including a set of items for each net that represent the net's routable elements. Each net's topological route specifies an associated set of items in the topological graph.

Abstract: Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a line. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method projects vectors from points on the first state that are locations of inflection points in the first PLF. At any intersection of the line and one of the vectors, the method computes a cost. The method also computes a cost at any endpoint of the line that does not intersect one of the vectors. Based on the computed costs, the method then specifies a second PLF that is defined over the second state.

Abstract: The present invention introduces several methods for implementing arbitrary angle wiring layers for integrated circuit manufacture with simulated Euclidean wiring. Entire routing layers may be implemented with arbitrary angle preferred wiring using simulated Euclidean wiring. In a first embodiment, the arbitrary angle wiring layers are created by routing arbitrary angle wires created from a selected ratio alternating segments of horizontal interconnect wire segments and vertical interconnect wire segments. In another embodiment, the arbitrary angle wiring layers are created by routing arbitrary angle wires created from a selected ratio alternating segments of horizontal interconnect wire segments and diagonal interconnect wire segments.

Abstract: Some embodiments of the invention provide a method for identifying locations of potential via between two layers of a design layout. The method identifies on one layer a first non-rectangular polygonal region for containing the via, and identifies on the other layer a second non-rectangular polygonal region for containing the via. It then determines whether an intersection of the first and second regions is sufficiently large to contain a via. If the intersection is sufficiently large, the method identifies the intersection of the two regions as a region for containing a via.

Abstract: Some embodiments of the invention provide a method for identifying topological routes in a multi-layer region of a design layout. The method selects a first net that has several routable elements. For the selected net, it then specifies a first multi-layer topological route that connects the first net's routable elements before selecting another net for routing. The first topological route traverses a plurality of layers. In addition, a topological route is a route that represents a set of diffeomorphic geometric routes.

Abstract: Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ.

Abstract: The present invention introduces several methods for laying out integrated circuit designs that use gridless non Manhattan routing to connect the integrated circuit components. In one embodiment, the non Manhattan routed integrated circuit designs are laid out by creating an initial route and then compacting the design down. In another embodiment, gridless non Manhattan integrated circuits are laid out by adapting a gridless Manhattan routing system into a gridless non Manhattan routing system by rotating a plane of a tile based maze router.

Abstract: Some embodiments of the invention provide a method of identifying routes for net in a region of a design layout. The method identifies a first route for a first net without using a routing grid. It then updates at least one previously defined route for another net to account for spacing constraints relating to the first route. In some embodiments, the method further (1) identifies previously defined routes that might need to be modified to account for spacing constraints relating to the first route; (2) examines the identified routes to determine whether the identified routes need to be modified to account for spacing constraints relating to the first route; and (3) updates several previously defined routes to account for spacing constraints relating to the first route.

Abstract: Some embodiments provide a method of propagating a first function, which is defined over a first state, to a second state in a multi-state space. The method identifies vectors to project from at least some points on the first state that serve as locations of inflection points in the first function; where the vectors are identified based on a model that allows penalizes measurements in certain directions more than other directions. Based on the projected vectors, the method then computes the second function from the first function.

Abstract: Some embodiments of the invention provide a method of routing a set of nets. The method specifies a first order for the set of nets. It then routes the nets according to the specified first order. The method then specifies a second order for the set of nets, where the second order has the fewest possible number of differences with the first order. The method then routes the nets according to the specified second order.

Abstract: Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ.

Abstract: One embodiment of the invention is a method of specifying routes for a group of nets. The method specifies a total cost. It then performs a first depth-first search to identify, for the group of nets, a complete routing solution that has a cost that does not exceed the total cost. A routing solution for a set of nets includes a route for each net in the set. If the search does not find the complete routing solution, the method then increments the total cost and performs a second depth-first search to identify a complete routing solution for the group of nets that has a cost that does not exceed the incremented total cost.

Abstract: Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ.

Abstract: Some embodiments of the invention provide a method of generating a multi-layer topological path for a layout that has multiple layers. This method specifies a set of path expansions from a first topological item to a second topological item on a first layer of the layout. For a potential via expansion from the second topological item to a third topological item on a second layer of the layout, the method (1) identifies a first region on the first layer for the second topological item, (2) identifies a second region on the second layer the third topological item, (3) determines whether an intersection of the first and second regions is sufficiently large to contain a via, and (4) if the intersection is sufficiently large, adds the potential via expansion to the specified set of path expansions.

Abstract: The present invention introduces several methods for implementing non Manhattan routing systems for integrated circuit manufacture. In one embodiment, a non Manhattan routing system is implemented by memorizing where intersections between wiring pitch grids occur and connecting such intersections with vias. In another embodiment, a gridless non Manhattan routing systems may be implemented by adapting a gridless Manhattan routing system by rotating a plane of a tile based maze router.