Patents by Inventor Andrew F. Glew

Andrew F. Glew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190108332
    Abstract: An embodiment or embodiments of an electronic device can comprise an input interface and a hardware component coupled to the input interface. The input interface can be operable to receive a plurality of taint indicators corresponding to at least one of a plurality of taints indicative of potential security risk which are injected from at least one of a plurality of resources. The hardware component can be operable to track the plurality of taints.
    Type: Application
    Filed: October 6, 2017
    Publication date: April 11, 2019
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Patent number: 9997495
    Abstract: A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first layer of high permeability material is deposited on the first silicon substrate that has the first inductive loop forming a first high permeability structure. The circuit further includes a second silicon substrate having a second inductive loop. A magnetic coupling is formed between the first inductive loop and the second inductive loop. The first high permeability structure can enhance the magnetic coupling between the first inductive loop and the second inductive loop. In some embodiments, a second layer of the high permeability material is deposited on the second silicon substrate that has the second inductive loop forming a second high permeability structure. The first high permeability structure and the second high permeability structure can form a magnetic circuit coupling the first inductive loop and the second inductive loop.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 12, 2018
    Assignee: Elwha LLC
    Inventors: Douglas C. Burger, William Gates, Andrew F. Glew, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, John L. Manferdelli, Thomas M. McWilliams, Craig J. Mundie, Nathan P. Myhrvold, Burton J. Smith, Clarence T. Tegreene, Thomas A. Weaver, Richard T. Witek, Lowell L. Wood, Jr., Victoria Y. H. Wood
  • Patent number: 9813445
    Abstract: An embodiment or embodiments of an electronic device can comprise an input interface and a hardware component coupled to the input interface. The input interface can be operable to receive a plurality of taint indicators corresponding to at least one of a plurality of taints indicative of potential security risk which are injected from at least one of a plurality of resources. The hardware component can be operable to track the plurality of taints.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: November 7, 2017
    Assignee: Elwha LLC
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Publication number: 20170293486
    Abstract: A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 12, 2017
    Inventors: Ranjit J. Rozario, Andrew F. Glew, Sanjay Patel, James Robinson, Sudhakar Ranganathan
  • Patent number: 9558034
    Abstract: An embodiment or embodiments of an information handling apparatus can use an entitlement vector to simultaneously manage and activate entitlement of objects and processes to various resources independently from one another. An information handling apparatus can comprise an entitlement vector operable to specify resources used by at least one object of a plurality of object. The information handling apparatus can further comprise a scheduler operable to schedule a plurality of threads based at least partly on entitlement as specified by the entitlement vector.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: January 31, 2017
    Assignee: Elwha LLC
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Patent number: 9554487
    Abstract: A apparatus for controlling heat transfer between portions of a substrate is provided. The apparatus includes a substrate including at least part of a hydraulic circuit, the hydraulic circuit including a plurality of microconduits, the plurality of microconduits including a first microconduit and a second microconduit. The apparatus further includes a liquid metal flowing through the hydraulic circuit and a magnetic field configured to selectively direct the flow of the liquid metal between the plurality of microconduits. The flow of the liquid metal through the hydraulic circuit transfers heat between a first portion of the substrate and the liquid metal.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: January 24, 2017
    Assignee: Elwha LLC
    Inventors: Andrew F. Glew, Roderick A. Hyde, Jordin T. Kare, Lowell L. Wood, Jr.
  • Publication number: 20160277441
    Abstract: An embodiment or embodiments of an electronic device can comprise an input interface and a hardware component coupled to the input interface. The input interface can be operable to receive a plurality of taint indicators corresponding to at least one of a plurality of taints indicative of potential security risk which are injected from at least one of a plurality of resources. The hardware component can be operable to track the plurality of taints.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 22, 2016
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Publication number: 20160181227
    Abstract: A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first layer of high permeability material is deposited on the first silicon substrate that has the first inductive loop forming a first high permeability structure. The circuit further includes a second silicon substrate having a second inductive loop. A magnetic coupling is formed between the first inductive loop and the second inductive loop. The first high permeability structure can enhance the magnetic coupling between the first inductive loop and the second inductive loop. In some embodiments, a second layer of the high permeability material is deposited on the second silicon substrate that has the second inductive loop forming a second high permeability structure. The first high permeability structure and the second high permeability structure can form a magnetic circuit coupling the first inductive loop and the second inductive loop.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Applicant: Elwha LLC
    Inventors: Douglas C. Burger, William Gates, Andrew F. Glew, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, John L. Manferdelli, Thomas M. McWilliams, Craig J. Mundie, Nathan P. Myhrvold, Burton J. Smith, Clarence T. Tegreene, Thomas A. Weaver, Richard T. Witek, Lowell L. Wood,, JR., Victoria Y.H. Wood
  • Publication number: 20160098279
    Abstract: Various embodiments are described relating to processors, hierarchical processors, branch predictors, branch prediction systems, and computing systems. Some or all of a hierarchical instruction scheduler, hierarchical register file, or a hierarchical store buffer may be included in a hierarchical microprocessor. Some or all aspects of the hierarchical microprocessor may be implemented, partially or fully, using a method for sequential data storage.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 7, 2016
    Inventor: Andrew F. Glew
  • Patent number: 9298918
    Abstract: An embodiment or embodiments of an electronic device can comprise an input interface and a hardware component coupled to the input interface. The input interface can be operable to receive a plurality of taint indicators corresponding to at least one of a plurality of taints indicative of potential security risk which are injected from at least one of a plurality of resources. The hardware component can be operable to track the plurality of taints.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: March 29, 2016
    Assignee: Elwha LLC
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Patent number: 9098608
    Abstract: An embodiment or embodiments of an information handling apparatus are adapted to facilitate resource allocation using an entitlement vector comprising multiple fields that are respectively directed to multiple different resources or capabilities. In illustrative embodiments, an information handling apparatus can comprise an entitlement vector configured with a plurality of bit fields at least partly corresponding to a plurality of resources and operable to specify the resources used by at least one object of a plurality of a plurality of objects. The information handling apparatus can further comprise logic operable to allocate the resources to the at least one object based on entitlement as specified by the entitlement vector.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: August 4, 2015
    Assignee: Elwha LLC
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Publication number: 20150128262
    Abstract: An embodiment or embodiments of a computing system can be adapted to manage security risk by accumulating and monitoring taint indications, and can respond to predetermined taint conditions detecting by the monitoring. An illustrative computing system can comprise a plurality of resources operationally coupled into the computing system, and at least one taint vector operable to list a plurality of taints indicative of potential security risk associated with a selected location and granularity of selected ones of the plurality of resources.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 7, 2015
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Patent number: 8955111
    Abstract: A processor is adapted to manage security risk by updating and monitoring a taint storage element in response to receipt of taint indicators, and responding to predetermined taint conditions detecting by the monitoring. The processor can be operable to execute instructions of a defined instruction set architecture and comprises an instruction of the instruction set architecture operable to access data from a source and operable to receive a taint indicator indicative of potential security risk associated with the data. The processor can further comprise a taint storage element operable for updating in response to receipt of the taint indicator and logic. The logic can be operable to update the taint storage element, process the taint storage element, determine a security risk condition based on the processing of the taint storage element, and respond to the security risk condition.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: February 10, 2015
    Assignee: Elwha LLC
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Patent number: 8943313
    Abstract: A data processing system, a server such as a federated server, a computer system, and like devices, and associated operating methods can be configured to support fine-grained security including resource allocation and resource scheduling. A data processing system can comprise a federated server operable to access data distributed among a plurality of remote data sources upon request from a plurality of client users and applications; and logic executable on the federated server. The logic can be operable to enforce fine-grained security operations on a plurality of federated shared data sets distributed among the plurality of remote data sources.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: January 27, 2015
    Assignee: Elwha LLC
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Publication number: 20150020075
    Abstract: An embodiment or embodiments of an information handling apparatus can use an entitlement vector to simultaneously manage and activate entitlement of objects and processes to various resources independently from one another. An information handling apparatus can comprise an entitlement vector operable to specify resources used by at least one object of a plurality of object. The information handling apparatus can further comprise a scheduler operable to schedule a plurality of threads based at least partly on entitlement as specified by the entitlement vector.
    Type: Application
    Filed: July 18, 2014
    Publication date: January 15, 2015
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Patent number: 8930714
    Abstract: A memory device is operable to perform channel encryption wherein for communication between devices, each includes cryptographic logic and performs cryptographic operations. In an illustrative embodiment, the memory device can comprise memory operable to store data communicated via a communication channel from a processor, and logic operable to perform channel encryption operations on the communication channel that communicates information between the processor and the memory.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: January 6, 2015
    Assignee: Elwha LLC
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Casey T. Tegreene
  • Patent number: 8904045
    Abstract: Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Andrew F. Glew
  • Patent number: 8813085
    Abstract: An embodiment or embodiments of an information handling apparatus can use an entitlement vector to simultaneously manage and activate entitlement of objects and processes to various resources independently from one another. An information handling apparatus can comprise an entitlement vector operable to specify resources used by at least one object of a plurality of object. The information handling apparatus can further comprise a scheduler operable to schedule a plurality of threads based at least partly on entitlement as specified by the entitlement vector.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: August 19, 2014
    Assignee: Elwha LLC
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Publication number: 20140223141
    Abstract: In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.
    Type: Application
    Filed: December 29, 2011
    Publication date: August 7, 2014
    Inventors: Jonathan D. Combs, Jason W. Brandt, Benjamin C. Chaffin, Julio Gago, Andrew F. Glew
  • Patent number: 8635415
    Abstract: A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: January 21, 2014
    Assignee: Intel Corporation
    Inventors: Baiju V. Patel, Rajeev Gopalakrishna, Andrew F. Glew, Robert J. Kushlis, Don Alan Van Dyke, Joseph Frank Cihula, Asit K. Mallick, James B. Crossland, Gilbert Neiger, Scott Dion Rodgers, Martin Guy Dixon, Mark Jay Charney, Jacob (Koby) Gottlieb