Patents by Inventor Andrew J. Walker

Andrew J. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10441828
    Abstract: A powered air purifying respirator (PAPR) for delivering a forced flow of filtered air to a wearer is disclosed.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: October 15, 2019
    Assignee: 3M Innovative Properties Company
    Inventors: Desmond T. Curran, Andrew Murphy, Garry J. Walker, Terence M. Sayers, Christopher P. Henderson, Bengt Kallman
  • Patent number: 10438999
    Abstract: A switching device, according to one embodiment, includes: a cylindrical pillar gate contact, an annular cylindrical channel which encircles a portion of the cylindrical pillar gate contact, an annular cylindrical oxide layer which encircles a portion of the annular cylindrical channel, and a source contact tab which encircles a portion of the annular cylindrical channel toward a first end of the annular cylindrical channel. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved annular cylindrical channel structures, improved source contacts, and/or improved cylindrical pillar gate contacts. These improved systems and components thereof may be implemented in vertical annular transistor structures in comparison to conventional surface transistor structures.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 8, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Gian Sharma, Amitay Levi, Andrew J. Walker, Kuk-Hwan Kim, Dafna Beery
  • Patent number: 10408693
    Abstract: Various sensor systems are described herein, including inserts having sensors thereon, which are configured to be received in an article of footwear. The inserts may be connected to a sole member of the footwear, or may function as a sole member. The sensors may be bonded to an outer surface of the insert, or positioned within the insert, in some configurations. The system may also include an electronic module that is overmolded into the sole structure and includes a connector for external access.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: September 10, 2019
    Assignee: NIKE, Inc.
    Inventors: Michael S. Amos, Frederick J. Dojan, Daniel Johnson, James C. Meschter, Matthew A. Nurse, Andrew A. Owings, Jeffrey C. Pisciotta, Allan M. Schrock, Steven H. Walker
  • Patent number: 10406287
    Abstract: Systems and methods are disclosed that provide smart alerts to users, e.g., alerts to users about diabetic states that are only provided when it makes sense to do so, e.g., when the system can predict or estimate that the user is not already cognitively aware of their current condition, e.g., particularly where the current condition is a diabetic state warranting attention. In this way, the alert or alarm is personalized and made particularly effective for that user. Such systems and methods still alert the user when action is necessary, e.g., a bolus or temporary basal rate change, or provide a response to a missed bolus or a need for correction, but do not alert when action is unnecessary, e.g., if the user is already estimated or predicted to be cognitively aware of the diabetic state warranting attention, or if corrective action was already taken.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: September 10, 2019
    Assignee: DexCom, Inc.
    Inventors: Anna Leigh Davis, Scott M. Belliveau, Naresh C. Bhavaraju, Leif N. Bowman, Rita M. Castillo, Alexandra Elena Constantin, Rian Draeger, Laura J. Dunn, Gary Brian Gable, Arturo Garcia, Thomas Hall, Hari Hampapuram, Christopher Robert Hannemann, Anna Claire Harley-Trochimczyk, Nathaniel David Heintzman, Andrea J. Jackson, Lauren Hruby Jepson, Apurv Ullas Kamath, Katherine Yerre Koehler, Aditya Sagar Mandapaka, Samuel Jere Marsh, Gary A. Morris, Subrai Girish Pai, Andrew Attila Pal, Nicholas Polytaridis, Philip Thomas Pupa, Eli Reihman, Ashley Anne Rindfleisch, Sofie Wells Schunk, Peter C. Simpson, Daniel Smith, Stephen J. Vanslyke, Matthew T. Vogel, Tomas C. Walker, Benjamin Elrod West, Atiim Joseph Wiley
  • Patent number: 10391337
    Abstract: A respirator assembly has a shell that defines a breathable air space for a user wearing the respirator assembly. The respirator assembly has an air delivery conduit within the shell for providing air to the breathable air space. The air delivery conduit has an air outlet that is either adjustable in configuration or has a vane associated therewith that is adjustable in position so that the direction of the air exiting the air outlet is controllable between first and second air flow directions. The user is able to control the direction of air exiting the air outlet while the respirator assembly is worn by the user.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: August 27, 2019
    Assignee: 3M Innovative Properties Company
    Inventors: Desmond T. Curran, Andrew Murphy, Garry J. Walker
  • Patent number: 10355046
    Abstract: According to one embodiment, an apparatus includes a bottom electrode layer positioned above a substrate in a film thickness direction, a source layer positioned above the bottom electrode layer in the film thickness direction, an impact ionization channel (i-channel) layer positioned above the source layer in the film thickness direction, a drain layer positioned above the i-channel layer in the film thickness direction, an upper electrode layer positioned above the drain layer in the film thickness direction that forms a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is positioned closer to the drain layer than the source layer. Other apparatuses are described in accordance with more embodiments.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 16, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10355045
    Abstract: According to one embodiment, an apparatus includes: a substrate, an array of 3D structures, where each 3D structure includes a source region having a first conductivity, a series of layers positioned in a vertical direction, a channel material on a surface of at least one sidewall of each 3D structure, and a gate dielectric material on the channel material. The series of layers includes a dielectric layer positioned above the substrate, a plurality of a set of MTJ layers positioned above the dielectric layer, and a buffer layer positioned in between the dielectric layer and each set of MTJ layers thereof. The magnetic memory device further includes an isolation region positioned between the 3D structures and at least one gate region positioned above the isolation region, where each gate region is coupled to at least one sidewall of each 3D structure.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 16, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10355047
    Abstract: A method, according to one embodiment, includes: forming an annular cylindrical channel from a single block of electrically conductive material; forming an oxide layer over exposed surfaces of the annular cylindrical channel and exposed surfaces of the block of electrically conductive material; removing a portion of the oxide layer from an exterior base of the annular cylindrical channel, thereby forming a source contact recess which surrounds the base of the annular cylindrical channel; ion-implanting the exposed electrically conductive material substrate at a base of the source contact recess; and depositing a silicide material in the source contact recess, thereby forming a source contact tab.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 16, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Gian Sharma, Amitay Levi, Andrew J. Walker, Kuk-Hwan Kim, Dafna Beery
  • Publication number: 20190214551
    Abstract: According to one embodiment, a method includes forming an etch-stop layer above a substrate, forming a matrix layer above the etch-stop layer, forming a set of pillars above the matrix layer, the set of pillars having a predefined spacing therebetween along a plane in an element width direction and an element depth direction, the plane being normal to a film thickness direction, forming a functionalization layer above the pillars, along sides of the pillars, and above the matrix layer, forming first diblock copolymer layers above the functionalization layer, the first diblock copolymer layers self-segregating into a first polymer and a second polymer in a first pattern, removing the first polymer from the first diblock copolymer layers to create a first mask layer, and removing portions of the matrix layer to expose portions of the etch-stop layer positioned therebelow and create a second pattern in the matrix layer.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 11, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10347311
    Abstract: A switching device, according to one embodiment, includes: a cylindrical pillar; an annular cylindrical oxide layer which encircles a portion of the cylindrical pillar; an annular cylindrical gate contact which encircles a portion of the annular cylindrical oxide layer; and a source contact which encircles a portion of the cylindrical pillar toward a first end of the cylindrical pillar. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved cylindrical gate contacts, improved source contacts, and/or improved drain contacts. These improved systems and components thereof may be implemented in vertical transistor structures which also include the aforementioned cylindrical pillar and cylindrical gate contact in comparison to conventional surface transistor structures.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 9, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Gian Sharma, Amitay Levi, Andrew J. Walker, Kuk-Hwan Kim, Dafna Beery
  • Patent number: 10347822
    Abstract: A method of forming a cylindrical vertical transistor; the method, according to one embodiment, includes: forming a cylindrical pillar from a single block of silicon, forming an oxide layer over an exterior of the cylindrical pillar and exposed surfaces of the block of silicon, coating the oxide layer with a spin-on-glass (SOG), depositing a source mask over a majority of the SOG coating, and removing a portion of the SOG coating and underlying oxide layer, where the portion removed is defined by the source mask. Other systems and methods are also described in additional embodiments herein which provide various different improved processes of forming the cylindrical gate contacts, the source contacts, and/or the drain contacts for vertical transistor structures which also include the aforementioned cylindrical pillar channel structures and cylindrical gate in comparison to conventional surface transistor structures.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 9, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Gian Sharma, Amitay Levi, Andrew J. Walker, Kuk-Hwan Kim, Dafna Beery
  • Publication number: 20190206935
    Abstract: According to one embodiment, an apparatus includes a bottom electrode layer positioned above a substrate in a film thickness direction, a source layer positioned above the bottom electrode layer in the film thickness direction, an impact ionization channel (i-channel) layer positioned above the source layer in the film thickness direction, a drain layer positioned above the i-channel layer in the film thickness direction, an upper electrode layer positioned above the drain layer in the film thickness direction that forms a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is positioned closer to the drain layer than the source layer. Other apparatuses are described in accordance with more embodiments.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20190206934
    Abstract: According to one embodiment, an apparatus includes: a substrate, an array of 3D structures, where each 3D structure includes a source region having a first conductivity, a series of layers positioned in a vertical direction, a channel material on a surface of at least one sidewall of each 3D structure, and a gate dielectric material on the channel material. The series of layers includes a dielectric layer positioned above the substrate, a plurality of a set of MTJ layers positioned above the dielectric layer, and a buffer layer positioned in between the dielectric layer and each set of MTJ layers thereof. The magnetic memory device further includes an isolation region positioned between the 3D structures and at least one gate region positioned above the isolation region, where each gate region is coupled to at least one sidewall of each 3D structure.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20190206940
    Abstract: According to one embodiment, a method includes forming a first insulative layer above a bottom surface of a groove and along inner sidewalls thereof, forming a source line layer within the groove of the substrate, forming a first dielectric layer on outer sides of a middle portion of the source line layer, forming a buffer layer on outer sides of the first dielectric layer, forming a gate terminal above the source line layer, forming a gate dielectric layer between the source line layer and the gate terminal and on outer sides of the lower portion of the gate terminal, forming a drain terminal including strained Si on outer sides of the first dielectric layer, and forming a relaxed buffer layer on outer sides of the upper portion of the source line layer and outer sides of the drain terminal, with the gate terminal extending beyond the relaxed buffer layer thickness.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20190207024
    Abstract: A transistor structure, according to one embodiment, includes: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel. The second side of the vertical channel is opposite the first side of the vertical channel along a plane perpendicular to a deposition direction. A magnetic device, according to another embodiment, includes: a plurality of transistor structures, each of the transistor structures comprising: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20190206938
    Abstract: A switching device, according to one embodiment, includes: a cylindrical pillar gate contact, an annular cylindrical channel which encircles a portion of the cylindrical pillar gate contact, an annular cylindrical oxide layer which encircles a portion of the annular cylindrical channel, and a source contact tab which encircles a portion of the annular cylindrical channel toward a first end of the annular cylindrical channel. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved annular cylindrical channel structures, improved source contacts, and/or improved cylindrical pillar gate contacts. These improved systems and components thereof may be implemented in vertical annular transistor structures in comparison to conventional surface transistor structures.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Gian Sharma, Amitay Levi, Andrew J. Walker, Kuk-Hwan Kim, Dafna Beery
  • Publication number: 20190206937
    Abstract: A method, according to one embodiment, includes: forming an annular cylindrical channel from a single block of electrically conductive material; forming an oxide layer over exposed surfaces of the annular cylindrical channel and exposed surfaces of the block of electrically conductive material; removing a portion of the oxide layer from an exterior base of the annular cylindrical channel, thereby forming a source contact recess which surrounds the base of the annular cylindrical channel; ion-implanting the exposed electrically conductive material substrate at a base of the source contact recess; and depositing a silicide material in the source contact recess, thereby forming a source contact tab.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Gian Sharma, Amitay Levi, Andrew J. Walker, Kuk-Hwan Kim, Dafna Beery
  • Publication number: 20190206716
    Abstract: A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20190206463
    Abstract: A magnetic device, according to one approach, includes: a plurality of perpendicular magnetic tunnel junction (p-MTJ) cells, each p-MTJ cell having a transistor and a magnetic tunnel junction (MTJ) sensor. Moreover, each of the transistors includes a drain terminal, a source terminal, and a gate terminal. The magnetic device also includes: a first common word line coupled to the gate terminal of each transistor in a first subset of the plurality of p-MTJ cells, a first common bit line coupled to a first end of each MTJ sensor in a second subset of the plurality of p-MTJ cells, and a first common source line coupled to the drain terminal of each transistor in the first subset. A second end of each of the MTJ sensors in the second subset is coupled to the source terminal of each respective transistor in the second subset.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Gian Sharma, Marcin Gajek, Kadriye Deniz Bozdag, Girish Jagtiani, Eric Michael Ryan, Michail Tzoufras, Amitay Levi, Andrew J. Walker
  • Publication number: 20190206941
    Abstract: A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker