Abstract: A structure for providing an inverter circuit employing two vertical transistor structures formed on a semiconductor substrate. The vertical semiconductor structures each include a semiconductor pillar structure and a surrounding gate dielectric. A gate structure is formed to at least partially surround the first and second vertical transistor structures. The semiconductor substrate is formed into first and section regions that are separated by a dielectric isolation structure. The first region includes a P+ doped portion and an N+ doped portion, and the second region includes an N+ doped portion and a P+ doped portion. The N+ and P+ doped portions of the first and second regions can be arranged such that the N+ doped portion of the first region is adjacent to the P+ doped portion of the second region, and the P+ doped portion of the first region is adjacent to the N+ doped portion of the second region.

Abstract: A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer.

Abstract: A transistor structure, according to one embodiment, includes: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel. The second side of the vertical channel is opposite the first side of the vertical channel along a plane perpendicular to a deposition direction. A magnetic device, according to another embodiment, includes: a plurality of transistor structures, each of the transistor structures comprising: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel.

Abstract: A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure can be tungsten (W). In addition, a thin layer of Ti or TiN can be formed between the metal gate layer and the first and second dielectric layers and the gate dielectric layer. The metal gate layer can be formed with or without the use of a sacrificial layer.

Abstract: A DRAM memory cell and memory cell array incorporating a metal silicide bit line buried within a doped portion of a semiconductor substrate and a vertical semiconductor structure electrically connected with a memory element such as a capacitive memory element. The buried metal silicide layer functions as a bit buried bit line which can provide a bit line voltage to the capacitive memory element via the vertical transistor structure. The buried metal silicide layer can be formed by allotaxy or mesotaxy. The vertical semiconductor structure can be formed by epitaxially growing a semiconductor material on an etched surface of the doped portion of the semiconductor substrate.

Abstract: A structure for providing an inverter circuit employing two vertical transistor structures formed on a semiconductor substrate. The vertical semiconductor structures each include a semiconductor pillar structure and a surrounding gate dielectric. A gate structure is formed to at least partially surround the first and second vertical transistor structures. The semiconductor substrate is formed into first and section regions that are separated by a dielectric isolation structure. The first region includes a P+ doped portion and an N+ doped portion, and the second region includes an N+ doped portion and a P+ doped portion. The N+ and P+ doped portions of the first and second regions can be arranged such that the N+ doped portion of the first region is adjacent to the P+ doped portion of the second region, and the P+ doped portion of the first region is adjacent to the N+ doped portion of the second region.

Abstract: A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer.

Abstract: A magnetic memory structure that includes a two-terminal resistive memory element electrically connected with a selector structure. The selector structure includes a semiconductor pillar structure formed on a semiconductor substrate. The selector structure is surrounded by a gate dielectric layer, and the semiconductor pillar structure and gate dielectric layer are surrounded by an electrically conductive gate structure. The semiconductor pillar has first and second dimensions in a plane parallel with the surface of the semiconductor substrate that are unequal with one another. The semiconductor pillar structure can have a cross-section parallel with the semiconductor substrate surface that is in the shape of a: rectangle; oval elongated polygon, etc. The length of the longer dimension can be adjusted to provide a desired amount of current though the semiconductor pillar structure to drive the two-terminal resistive memory element.

Abstract: A magnetic memory array having an epitaxially grown vertical semiconductor selector connected with a two terminal resistive switching memory element via a bottom electrode such as TaN. An electrically conductive contact such as tungsten (W) or TaN can be included between the vertical semiconductor channel and the TaN bottom electrode. The electrically conductive contact and the TaN bottom electrode can both be formed by a damascene process wherein an opening is formed in an oxide layer and a metal is deposited into the opening. A chemical mechanical polishing process can then be performed to remove portions of the metal that extend out of the opening in the oxide layer over the oxide surface.

Abstract: A magnetic memory array having an epitaxially grown vertical semiconductor selector connected with a two terminal resistive switching memory element via a bottom electrode such as TaN. An electrically conductive contact such as tungsten (W) or TaN can be included between the vertical semiconductor channel and the TaN bottom electrode. The electrically conductive contact and the TaN bottom electrode can both be formed by a damascene process wherein an opening is formed in an oxide layer and a metal is deposited into the opening. A chemical mechanical polishing process can then be performed to remove portions of the metal that extend out of the opening in the oxide layer over the oxide surface.

Abstract: A magnetic memory array having an epitaxially grown vertical semiconductor selector connected with a memory element via a bottom electrode such as TaN. An electrically conductive contact such as tungsten (W) or TaN can be included between the vertical semiconductor channel and the TaN bottom electrode. The electrically conductive contact and the TaN bottom electrode can both be formed by a damascene process wherein an opening is formed in an oxide layer and a metal is deposited into the opening. A chemical mechanical polishing process can then be performed to remove portions of the metal that extend out of the opening in the oxide layer over the oxide surface.

Abstract: A magnetic memory array having an epitaxially grown vertical semiconductor selector connected with a memory element via a bottom electrode such as TaN. An electrically conductive contact such as tungsten (W) or TaN can be included between the vertical semiconductor channel and the TaN bottom electrode. The electrically conductive contact and the TaN bottom electrode can both be formed by a damascene process wherein an opening is formed in an oxide layer and a metal is deposited into the opening. A chemical mechanical polishing process can then be performed to remove portions of the metal that extend out of the opening in the oxide layer over the oxide surface.

Abstract: A method for crystalized silicon structures from amorphous structures in a magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.

Abstract: According to one embodiment, a method includes forming a first insulative layer above a bottom surface of a groove and along inner sidewalls thereof, forming a source line layer within the groove of the substrate, forming a first dielectric layer on outer sides of a middle portion of the source line layer, forming a buffer layer on outer sides of the first dielectric layer, forming a gate terminal above the source line layer, forming a gate dielectric layer between the source line layer and the gate terminal and on outer sides of the lower portion of the gate terminal, forming a drain terminal including strained Si on outer sides of the first dielectric layer, and forming a relaxed buffer layer on outer sides of the upper portion of the source line layer and outer sides of the drain terminal, with the gate terminal extending beyond the relaxed buffer layer thickness.

Abstract: A magnetic memory array having a source-plane electrically connected with an array of channel selectors in two-dimensions. The array of channel selectors can be arranged in rows and columns with both the rows and columns being electrically connected with a source-plane. A memory element such as a two terminal resistive switching memory element can be electrically connected with each of the channel selectors. The source-plane can include a doped region formed in a surface of a semiconductor substrate and may also include an electrically conductive layer formed on the doped region. The use of such a planar, two-dimensional source-plane allows for greatly increased data density by eliminating the need to form separate source-line source lines for individual rows of channel selectors.

Abstract: A magnetic memory array having a source-plane electrically connected with an array of channel selectors in two-dimensions. The array of channel selectors can be arranged in rows and columns with both the rows and columns being electrically connected with a source-plane. A magnetic memory element such as a magnetic tunnel junction element can be electrically connected with each of the channel selectors. The source-plane can include a doped region formed in a surface of a semiconductor substrate and may also include an electrically conductive layer formed on the doped region. The use of such a planar, two-dimensional source-plane allows for greatly increased data density by eliminating the need to form separate source-line source lines for individual rows of channel selectors.

Abstract: A method for forming three-dimensional magnetic memory arrays by forming crystalized silicon structures from amorphous structures in the magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.

Abstract: A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.

Abstract: A memory array for data recording that includes a selector transistor electrically connected with a two terminal resistive memory element such as a magnetic tunnel junction (MTJ) element. The selector transistor comprises a semiconductor column formed by selective epitaxial growth on a semiconductor surface. The semiconductor column is at least partially surrounded by a gate dielectric layer and an electrically conductive gate structure arranged such that the gate dielectric is between the electrically conducive gate structure and the semiconductor column. The selective epitaxial growth of the semiconductor column allows the semiconductor column to have a very low electrical resistance in an “on” state which allows the selector transistor to provide a high electrical current to the two terminal resistive memory element for reliable switching during data writing.

Abstract: According to one embodiment, a method of forming a magnetic memory device includes forming a source region including a first semiconductor material having a first conductivity above a substrate, forming an array of three-dimensional (3D) structures above the substrate, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material on the channel material on the surface of at least one sidewall of each 3D structure, forming a first isolation region in the cavity region above the substrate, forming a first gate region above the first isolation region in the cavity region, and forming a second isolation region above the first gate region, wherein a nth gate region is formed above a (n+1) isolation region thereafter until a top of the array of 3D structures, wherein each nth gate region is coupled to each nth perpendicular magnetic tunnel junction sensor of each 3D structure.