Patents by Inventor Andrew J. Walker

Andrew J. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190206935
    Abstract: According to one embodiment, an apparatus includes a bottom electrode layer positioned above a substrate in a film thickness direction, a source layer positioned above the bottom electrode layer in the film thickness direction, an impact ionization channel (i-channel) layer positioned above the source layer in the film thickness direction, a drain layer positioned above the i-channel layer in the film thickness direction, an upper electrode layer positioned above the drain layer in the film thickness direction that forms a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is positioned closer to the drain layer than the source layer. Other apparatuses are described in accordance with more embodiments.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20190206932
    Abstract: According to one embodiment, a method of forming a magnetic memory device includes forming a source region including a first semiconductor material having a first conductivity above a substrate, forming an array of three-dimensional (3D) structures above the substrate, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material on the channel material on the surface of at least one sidewall of each 3D structure, forming a first isolation region in the cavity region above the substrate, forming a first gate region above the first isolation region in the cavity region, and forming a second isolation region above the first gate region, wherein a nth gate region is formed above a (n+1) isolation region thereafter until a top of the array of 3D structures, wherein each nth gate region is coupled to each nth perpendicular magnetic tunnel junction sensor of each 3D structure.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20190206716
    Abstract: A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20190206463
    Abstract: A magnetic device, according to one approach, includes: a plurality of perpendicular magnetic tunnel junction (p-MTJ) cells, each p-MTJ cell having a transistor and a magnetic tunnel junction (MTJ) sensor. Moreover, each of the transistors includes a drain terminal, a source terminal, and a gate terminal. The magnetic device also includes: a first common word line coupled to the gate terminal of each transistor in a first subset of the plurality of p-MTJ cells, a first common bit line coupled to a first end of each MTJ sensor in a second subset of the plurality of p-MTJ cells, and a first common source line coupled to the drain terminal of each transistor in the first subset. A second end of each of the MTJ sensors in the second subset is coupled to the source terminal of each respective transistor in the second subset.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Gian Sharma, Marcin Gajek, Kadriye Deniz Bozdag, Girish Jagtiani, Eric Michael Ryan, Michail Tzoufras, Amitay Levi, Andrew J. Walker
  • Publication number: 20190206941
    Abstract: A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20190206938
    Abstract: A switching device, according to one embodiment, includes: a cylindrical pillar gate contact, an annular cylindrical channel which encircles a portion of the cylindrical pillar gate contact, an annular cylindrical oxide layer which encircles a portion of the annular cylindrical channel, and a source contact tab which encircles a portion of the annular cylindrical channel toward a first end of the annular cylindrical channel. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved annular cylindrical channel structures, improved source contacts, and/or improved cylindrical pillar gate contacts. These improved systems and components thereof may be implemented in vertical annular transistor structures in comparison to conventional surface transistor structures.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Gian Sharma, Amitay Levi, Andrew J. Walker, Kuk-Hwan Kim, Dafna Beery
  • Publication number: 20190207024
    Abstract: A transistor structure, according to one embodiment, includes: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel. The second side of the vertical channel is opposite the first side of the vertical channel along a plane perpendicular to a deposition direction. A magnetic device, according to another embodiment, includes: a plurality of transistor structures, each of the transistor structures comprising: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20190206937
    Abstract: A method, according to one embodiment, includes: forming an annular cylindrical channel from a single block of electrically conductive material; forming an oxide layer over exposed surfaces of the annular cylindrical channel and exposed surfaces of the block of electrically conductive material; removing a portion of the oxide layer from an exterior base of the annular cylindrical channel, thereby forming a source contact recess which surrounds the base of the annular cylindrical channel; ion-implanting the exposed electrically conductive material substrate at a base of the source contact recess; and depositing a silicide material in the source contact recess, thereby forming a source contact tab.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Gian Sharma, Amitay Levi, Andrew J. Walker, Kuk-Hwan Kim, Dafna Beery
  • Patent number: 10333063
    Abstract: According to one embodiment, a method includes forming an etch-stop layer above a substrate, forming a matrix layer above the etch-stop layer, forming a set of pillars above the matrix layer, the set of pillars having a predefined spacing therebetween along a plane in an element width direction and an element depth direction, the plane being normal to a film thickness direction, forming a functionalization layer above the pillars, along sides of the pillars, and above the matrix layer, forming first diblock copolymer layers above the functionalization layer, the first diblock copolymer layers self-segregating into a first polymer and a second polymer in a first pattern, removing the first polymer from the first diblock copolymer layers to create a first mask layer, and removing portions of the matrix layer to expose portions of the etch-stop layer positioned therebelow and create a second pattern in the matrix layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 25, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10243021
    Abstract: According to one embodiment, a method includes forming a bottom electrode layer above a substrate in a film thickness direction, forming a source layer above the bottom electrode layer in the film thickness direction, forming an impact ionization channel (i-channel) layer above the source layer in the film thickness direction, forming a drain layer above the i-channel layer in the film thickness direction, forming an upper electrode layer above the drain layer in the film thickness direction to form a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and forming a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is formed in a position closer to the drain layer than the source layer.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: March 26, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10186551
    Abstract: In one embodiment, an apparatus includes lower electrodes positioned below a surface of a substrate, the substrate including crystalline Si, a plurality of strap regions positioned above the lower electrodes and below sets of pillars of Si, the pillars rising above the substrate, the sets of pillars being aligned in a first direction along a plane perpendicular to a film thickness direction, and the strap regions extending above a surface of the substrate, silicide junctions positioned between each of the strap regions and a corresponding lower electrode positioned therebelow, upper electrodes positioned above each of the pillars, gate dielectric layers positioned on sides of the pillars to a height greater than a lower edge of the upper electrodes, and gate layers positioned on sides of the gate dielectric layers in a second direction along the plane and perpendicular to the first direction that transverse a plurality of sets of pillars.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: January 22, 2019
    Assignee: Spin Transfer Technologies, Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Gian Sharma, Amitay Levi, Andrew J. Walker
  • Patent number: 9953995
    Abstract: A memory array provided on a semiconductor substrate includes: (a) channel structures arranged in multiple layers above the semiconductor substrate, each channel structure extending along a first direction substantially parallel a surface of the semiconductor substrate; (b) gate structures each extending along a second direction substantially transverse to the first direction and each being adjacent one of the channel structures, separated therefrom by a layer of memory material; and (c) conductors provided to connect the gate structures with circuitry fabricated in the semiconductor substrate, wherein at each location where one of the gate structure adjacent one of the channel structures, a portion of the gate structure, a portion of the channel structure and the layer of memory material constitute a memory cell of the memory array. Two or more memory cells sharing a channel structure are connected in series to form a NAND string.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 24, 2018
    Assignee: SCHILTRON CORPORATION
    Inventor: Andrew J. Walker
  • Publication number: 20170278858
    Abstract: A monolithic 3-D dynamic memory structure includes independently addressable strings of dual-gate devices. In each dual-gate device charge is deliberately stored on one side of the dual-gate. Although the stored charge may leak away, the stored charge in a dual-gate device of the present invention need only be refreshed at much longer intervals than conventional DRAM cells.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 28, 2017
    Inventors: Andrew J. Walker, Eli Harari
  • Publication number: 20170025437
    Abstract: A memory array provided on a semiconductor substrate includes: (a) channel structures arranged in multiple layers above the semiconductor substrate, each channel structure extending along a first direction substantially parallel a surface of the semiconductor substrate; (b) gate structures each extending along a second direction substantially transverse to the first direction and each being adjacent one of the channel structures, separated therefrom by a layer of memory material; and (c) conductors provided to connect the gate structures with circuitry fabricated in the semiconductor substrate, wherein at each location where one of the gate structure adjacent one of the channel structures, a portion of the gate structure, a portion of the channel structure and the layer of memory material constitute a memory cell of the memory array. Two or more memory cells sharing a channel structure are connected in series to form a NAND string.
    Type: Application
    Filed: July 19, 2016
    Publication date: January 26, 2017
    Inventor: Andrew J. Walker
  • Publication number: 20160099355
    Abstract: A non-volatile memory device combines thin-film transistor-based memory cells with bulk mono-crystalline silicon transistors, which can more efficiently drive bit lines for fast sensing of the stored data in the thin-film memory cells.
    Type: Application
    Filed: May 6, 2015
    Publication date: April 7, 2016
    Inventor: Andrew J. Walker
  • Patent number: 8737027
    Abstract: A device for providing electrostatic discharge (ESD) protection is described which includes a silicon controlled rectifier (SCR), a mechanism for triggering the SCR, and a pair of contact regions of opposing conductivity type distinct from regions of the SCR that are interposed between the cathodic and anodic regions of the SCR. The contact regions are configured to collect charge generated by the SCR. In some embodiments, the device may include a transistor and the cathodic region of the SCR may dually serve as a source contact region of the transistor. A circuit is described which includes an ESD protection device coupled between high and low voltage power supply bus bars, wherein the ESD protection device includes an SCR as well as a pair of contact regions of opposing conductivity type distinct from the SCR and interposed between the cathodic and anodic regions of the SCR.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: May 27, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Andrew J. Walker
  • Patent number: 8637366
    Abstract: A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: January 28, 2014
    Assignee: Sandisk 3D LLC
    Inventors: S. Brad Herner, Andrew J. Walker
  • Patent number: 8278684
    Abstract: A voltage protection device and method is provided to prevent accidental triggering of an silicon-controlled rectifier (SCR) unless the electrostatic discharge (ESD) is at a predefined threshold above the normal power supply operating voltage or below the ground supply operating voltage. The holding voltage upon the SCR is maintained above the threshold voltage to prevent accidental triggering. The present SCR avoids use of an additional field effect transistor (FET), and avoids relying upon the breakdown of the drain terminal of the FET, but instead programs the amount of holding voltage needed above the power supply voltage using mask-programmability, fuses, or other means for maintaining the holding voltage to a desired range above the power supply voltage. The programmed holding voltage is implemented using a barrier region between the PNP and the NPN of the PNPN junctions of the SCR.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: October 2, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Andrew J. Walker, Helmut Puchner
  • Publication number: 20120223380
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Application
    Filed: May 10, 2012
    Publication date: September 6, 2012
    Applicant: SanDisk 3D LLC
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher J. Petti, Igor G. Kouznetzov, Mark G. Johnson, Paul Michael Farmwald, Brad Herner
  • Publication number: 20110156044
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 30, 2011
    Applicant: SanDisk 3D LLC
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher J. Petti, Igor G. Kouznetzov, Mark G. Johnson, Paul Michael Farmwald, Brad Herner