Abstract: An apparatus and method for write posting in a universal serial bus (USB) system includes a host computer connected to USB devices via a USB. The host computer generates requests to write data to memory within the USB device. The host computer includes a queue for posting the write requests on generation thereof. The write requests are posted in the queue until the host computer transmits a single data packet generated from the posted write requests. The Data packet is generated in response to the host computer generating a request to read data from the USB device, the host computer determining that the most recently posted write request is directed to a memory location within the USB device which is nonpostable, or an indication that the queue lacks storage space for subsequent write requests. The USB device receives the transmitted Data packet from the host computer and writes data to internal memory locations in accordance with the received Data packet.

Abstract: An apparatus and method is provided for caching data in a universal serial bus (USB) system. In one embodiment, the present invention employs a host computer coupled to an I/O device via a USB. The host computer includes a data cache for storing data retrieved from the I/O device. The data cache allows data to be returned to the host computer upon request without accessing the I/O device via a USB transaction. A cacheability look-up table and cache table are provided to ensure the integrity of data returned to the host computer. Requested data is returned from the I/O device if the cacheability look-up table indicates the requested data is noncacheable. Data is returned from the data cache if the cache table indicates the requested data is available in the cache as valid data. If the cache table indicates the requested data is not available in the cache as valid data, the requested data is returned from the I/O device along with data stored in predetermined I/O device addresses.

Abstract: A GPIB system for capturing GPIB signals at a predetermined rate and upon valid transitions of the data valid signal. A first sampling circuit samples the GPIB at the predetermined rate and a second sampling circuit samples the GPIB with transitions of the data valid signal. Capture logic preferably includes data valid logic for monitoring the data valid signal to assure valid transitions. The capture logic also preferably includes select logic for selecting between the GPIB signals sampled at the predetermined rate and upon assertion of the data valid signal, where data valid signal transitions preferably have higher priority. The capture logic monitors the sampled GPIB signals and the data valid logic to enable a first-in, first-out buffer to capture sampled data upon predetermined capture conditions and upon transitions of the data valid signal. In this manner, data signal transitions which might otherwise be missed by the predetermined sampling rate are sampled and captured.

Abstract: A deglitch circuit for filtering false transitions of an input signal based on transitions of a clock signal. A plurality of memory devices as provided for detecting the input signal being assay for two, three and five transitions of the clock signal in the preferred embodiment. Programmable select logic is also provided for selecting between these three cases. In the preferred embodiment, six separate flip-flops are included and clocked by the clocked signal, four of the flip-flops being reset upon spurious negations of the input signal for reign such transitions, and where two of the four flip-flops are clocked on the rising edge whereas the other two are clocked on the falling edge of the clock signal. The programmable select logic preferably includes a multiplexer for choosing between the three cases. In the preferred embodiment, the input signal is the data valid (DAV) signal of a GPIB, where the deglitch circuit assures valid data sampling on a GPIB.