Patents by Inventor Ankur Agrawal

Ankur Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134600
    Abstract: Provided are a floating-point unit, a system, and method for generating binary integer output or floating-point output based on a selector. A first input operand, a second input operand, a third input operand, and a result format selector value are received. The first input operand, the second input operand, and the third input operand comprise floating-point values. The first input operand, the second input operand, and the third input operand are processed to produce a final result comprising one of a binary integer value and a floating point value based on the result format selector value.
    Type: Application
    Filed: December 30, 2022
    Publication date: April 25, 2024
    Inventors: Ankur AGRAWAL, Kailash GOPALAKRISHNAN, Hung Hoang TRAN, Vijayalakshmi SRINIVASAN
  • Publication number: 20240134601
    Abstract: Provided are a floating-point unit, a system, and method for fused multiply-add logic to process input operands including floating-point values and integer values. A first input operand comprising an integer value and second and third input operands comprising floating-point values are received. The first, second, and third input operands are processed to produce a floating-point result.
    Type: Application
    Filed: November 11, 2022
    Publication date: April 25, 2024
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ankur AGRAWAL, Kailash GOPALAKRISHNAN
  • Patent number: 11894474
    Abstract: Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment the optoelectronic system comprises a board, and a carrier attached to the board. In an embodiment, a first die is on the carrier. In an embodiment, the first die is a photonics die, and a surface of the first die is covered by an optically transparent layer.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Priyanka Dobriyal, Ankur Agrawal, Susheel Jadhav, Quan Tran, Raghuram Narayan, Raiyomand Aspandiar, Kenneth Brown, John Heck
  • Publication number: 20240013871
    Abstract: A SaaS platform to manage a clinical trial is disclosed. The platform enables on-boarding of patients for the clinical trial for one or more clinical research organizations. Such details are necessary for categorisation of the one or more patients. A medical compliance module is set up to capture real time bio-physical parameters indicative of health condition of the patients. The medical compliance module also monitors adherence of each of the patients to the one or more treatment plans designed for the clinical trials. Additionally, a database management module receives, and stores data associated with the clinical trial from the one or more clinical research organisations. Storing of such classified data is being done with specific privacy level for security. An access control module further enables collaborative clinical trial among the one or more clinical research organisations by sharing the data associated with the clinical trial in real-time.
    Type: Application
    Filed: August 27, 2021
    Publication date: January 11, 2024
    Inventors: Vivek Asthana, Ankur Agrawal
  • Patent number: 11815954
    Abstract: Provided is a method, performed by an electronic device, of performing an operation based on bending, the method including: sensing bending that deforms a shape of the electronic device; determining a first region, from which the bending is sensed, from among regions of the electronic device; selecting an object indicated by the first region from at least one object displayed on the electronic device; and performing an operation on the selected object.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: November 14, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Vipul Gupta, Rahul Agrawal, Ankur Agrawal, Amit Agrawal, Kalgesh Singh, Saurabh Kumar, Ashutosh Raghuvanshi
  • Patent number: 11809837
    Abstract: A multiply-accumulate device comprises a digital multiplication circuit and a mixed signal adder. The digital multiplication circuit is configured to input L m1-bit multipliers and L m2-bit multiplicands and configured to generate N one-bit multiplication outputs, each one-bit multiplication output corresponding to a result of a multiplication of one bit of one of the L m1-bit multipliers and one bit of one of the L m2-bit multiplicands. The mixed signal adder comprises one or more stages, at least one stage configured to input the N one-bit multiplication outputs, each stage comprising one or more inner product summation circuits; and a digital reduction stage coupled to an output of a last stage of the one or more stages and configured to generate an output of the multiply-accumulate device based on the L m1-bit multipliers and the L m2-bit multiplicands.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: November 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Ankur Agrawal, Martin Cochet, Jonathan E. Proesel, Sergey Rylov, Bodhisatwa Sadhu, Hyunkyu Ouh
  • Patent number: 11811416
    Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: November 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kyu-hyoun Kim, Mingu Kang, Ankur Agrawal, Monodeep Kar
  • Publication number: 20230334206
    Abstract: Aspects of a storage device are provided for efficient handling of logical metablock formation based on a heat distribution within the storage device. The storage device includes a plurality of memory dies each including a physical block, and a controller which forms a logical metablock from the physical blocks based on a location of each of the memory dies with respect to the controller. The controller stores a mapping of heat credit points to each of the physical blocks, where each of the heat credit points are associated with a respective heat level. The controller forms logical metablocks from the physical blocks based on the mapping. For instance, the controller forms different logical metablocks from physical blocks based on respective heat levels associated with memory dies including those blocks. As a result, efficient logical block formation may be achieved without significant complexity in firmware implementation.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: Ramanathan Muthiah, Ankur Agrawal, Muralitharan Jayaraman
  • Publication number: 20230326567
    Abstract: A system to facilitate medical adherence is disclosed. The system includes a patient information recording module, configured to record information regarding at least one of one or more diseases, one or more bio-physical parameters, type of discomfort, severity of discomfort, part of body experiencing the discomfort and time of discomfort associated with registered patient via at least one of textual input, pre-designated field input and input on 3D image representative of human body. The system includes a medical treatment module, configured to diagnose the one or more diseases, generate a real-time treatment plan and generate a digital prescription for the registered patient. The system includes a medical adherence module, configured to monitor adherence of the registered patient to the real-time generated treatment plan at a micro level, create a medical adherence report and trigger an alert on an event of non-adherence of the real-time generated treatment plan.
    Type: Application
    Filed: August 27, 2021
    Publication date: October 12, 2023
    Inventors: Vivek Asthana, Ankur Agrawal
  • Publication number: 20230326585
    Abstract: A system to facilitate adherence to multiple medical care plans is disclosed. The system includes a consent management module, configured to classify the information received from the biophysical data capturing module and the health status recording module in accordance with predesignated privacy matrix level and configured to provide access to a specific privacy level of classified information associated with a specific disease to one of one or more doctors, upon receiving consent from at least one of one or more registered doctors, the registered patient and the one or more registered healthcare personnel. The system includes a graphic user interface module, configured to provide integrated view of the information, configured to enable the one or more registered doctors to collaboratively intervene according to information provided and also configured to enforce adherence of the registered patient to the one or more treatment plans.
    Type: Application
    Filed: August 27, 2021
    Publication date: October 12, 2023
    Inventors: Vivek Asthana, Ankur Agrawal
  • Publication number: 20230318247
    Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes multiple PICs in the package that are optically coupled with each other. In embodiments, the package may include discrete electronic and optical components, and thermal management solutions for co-packaging of multiple PICs. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Eleanor Patricia Paras RABADAM, Guiyun BAI, Sanjeev GUPTA, Ronald SPREITZER, Jonathan DOYLEND, Ankur AGRAWAL, Boping XIE, Sushrutha Reddy GUJJULA, Jason GARCIA, Kenneth BROWN, Dan WANG, Daniel GRODENSKY, Israel PETRONIUS, Konstantin MATYUCH
  • Patent number: 11775257
    Abstract: Techniques for operating on and calculating binary floating-point numbers using an enhanced floating-point number format are presented. The enhanced format can comprise a single sign bit, six bits for the exponent, and nine bits for the fraction. Using six bits for the exponent can provide an enhanced exponent range that facilitates desirably fast convergence of computing-intensive algorithms and low error rates for computing-intensive applications. The enhanced format can employ a specified definition for the lowest binade that enables the lowest binade to be used for zero and normal numbers; and a specified definition for the highest binade that enables it to be structured to have one data point used for a merged Not-a-Number (NaN)/infinity symbol and remaining data points used for finite numbers. The signs of zero and merged NaN/infinity can be “don't care” terms. The enhanced format employs only one rounding mode, which is for rounding toward nearest up.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: October 3, 2023
    Assignee: International Business Machines Corporation
    Inventors: Silvia Melitta Mueller, Ankur Agrawal, Bruce Fleischer, Kailash Gopalakrishnan, Dongsoo Lee
  • Patent number: 11715928
    Abstract: An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 1, 2023
    Assignee: Intel Corporation
    Inventors: Priyanka Dobriyal, Susheel G. Jadhav, Ankur Agrawal, Quan A. Tran, Raiyomand F. Aspandiar, Kenneth M. Brown
  • Patent number: 11699085
    Abstract: Logic may determine a specific performance of a neural network based on an event and may present the specific performance to provide a user with an explanation of the inference by a machine learning model such as a neural network. Logic may determine a first activation profile associated with the event, the first activation profile based on activation of nodes in one or more layers of the neural network during inference to generate an output. Logic may correlate the first activation profile against a second activation profile associated with a first training sample of training data. Logic may determine that the first training sample is associated with the event based on the correlation. Logic may output an indicator to identify the first training sample as being associated with the event.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Glen J. Anderson, Rajesh Poornachandran, Ignacio J. Alvarez, Giuseppe Raffa, Jill Boyce, Ankur Agrawal, Kshitij Arun Doshi
  • Publication number: 20230204877
    Abstract: Technologies for beam expansion and collimation for photonic integrated circuits (PICs) are disclosed. In one embodiment, an ancillary die is bonded to a PIC die. Vertical couplers in the PIC die direct light from waveguides to flat mirrors on a top side of the ancillary die. The flat mirrors reflect the light towards curved mirrors defined in the bottom surface of the ancillary die. The curved mirrors collimate the light from the waveguides. In another embodiment, a cavity is formed in a PIC die, and curved mirrors are formed in the cavity. Light beams from waveguides in the PIC die are directed to the curved mirrors, which collimate the light beams.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Applicant: Intel Corporation
    Inventors: John M. Heck, Haisheng Rong, Harel Frish, Ankur Agrawal, Boping Xie, Randal S. Appleton, Hari Mahalingam, Alexander Krichevsky, Pooya Tadayon, Ling Liao, Eric J. M. Moret
  • Publication number: 20230207412
    Abstract: Example techniques to enable a flip chip underfill exclusion zone include use of bump barriers, films or etched substrate cavities to prevent underfill from reaching the flip chip underfill exclusion zone.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Ronald SPREITZER, Jason GARCIA, Ankur AGRAWAL, Eleanor Patricia Paras RABADAM, Guiyun BAI
  • Publication number: 20230196537
    Abstract: A method for enhancing image quality using an electronic device is provided. The method includes receiving, by the electronic device, an image frame from a network, monitoring, by the electronic device, a network parameter of the network, determining, by the electronic device, a context of the electronic device, identifying, by the electronic device, a visual degradation in the image frame based on the monitored network parameter and the context of the electronic device, and modifying, by the electronic device, a visual quality factor of the image frame based on the visual degradation in the image frame for enhancing the image quality.
    Type: Application
    Filed: September 29, 2022
    Publication date: June 22, 2023
    Inventors: Vipul GUPTA, Ankur AGRAWAL, Vaibhav NEGI, Rahul AGRAWAL
  • Publication number: 20230197699
    Abstract: Various embodiments disclosed relate to semiconductor packaging for photonic modules in LiDAR systems. The present disclosure includes semiconductor assemblies using an organic substrate interposer surface mounted to the printed circuit board, with an electronic integrated circuit die attached to the organic substrate and a photonic integrated circuit die attached to the organic substrate, wherein the electronic integrated circuit die, and the photonic integrated circuit die are electrically coupled to each other through the organic substrate interposer.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Inventors: Ronald L. Spreitzer, Ankur Agrawal, Guiyun Bai, Eleanor Patricia Paras Rabadam, Sanjeev Gupta
  • Patent number: 11682206
    Abstract: Methods and apparatus for projecting augmented reality (AR) enhancements to real objects in response to user gestures detected in a real environment are disclosed. An example apparatus includes one or more processors to execute computer-readable instructions to identify a user gesture within a real environment based on data obtained from a motion sensor. The user gesture is associated with a target real object from among one or more real objects located within the real environment. The user gesture represents a desired shape of a desired virtual drawing to be projected to the target real object. The one or more processors are further to execute the instructions to determine an AR enhancement based on the user gesture and the target real object. The AR enhancement includes a virtual drawing having a shape corresponding to the desired shape of the desired virtual drawing.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Ankur Agrawal, Glen J. Anderson, Benjamin Bair, Rebecca Chierichetti, Pete Denman
  • Publication number: 20230188146
    Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Inventors: Kyu-hyoun Kim, Mingu Kang, Ankur Agrawal, Monodeep Kar