Patents by Inventor Ankur Agrawal

Ankur Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11030459
    Abstract: Methods and apparatus for projecting augmented reality (AR) enhancements to real objects in response to user gestures detected in a real environment are disclosed. An example apparatus includes an object detector, a gesture detector, and an enhancement determiner. The object detector is to detect one or more real objects located in a real environment based on depth data obtained from a sensor array located within the real environment. The gesture detector is to detect a user gesture within the real environment based on motion data obtained from the sensor array, the user gesture being associated with a target real object from among the one or more real objects. The enhancement determiner is to determine an AR enhancement based on the user gesture and the target real object. The enhancement determiner is to instruct a projector to project the AR enhancement to the target real object.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 8, 2021
    Assignee: INTEL CORPORATION
    Inventors: Ankur Agrawal, Glen J. Anderson, Benjamin Bair, Rebecca Chierichetti, Pete Denman
  • Patent number: 11024353
    Abstract: Aspects of a storage device including a controller, a calibration resistor and a die having an output driver and a calibration circuit are provided, which allow for an output impedance of the output driver to be calibrated to a lower impedance than a minimum required for reading data across PVT variations of the die at maximum loading of the controller. To check whether slow corners may operate using the lower impedance, the controller determines whether the output impedance of the output driver can be calibrated to the lower impedance at a maximum temperature and minimum voltage applied to the die, or whether a calibration code generated from the calibration circuit exceeds a threshold at a nominal temperature and voltage applied to the die. Thus, slow corners are screened out from lower impedance use, while faster devices are designed with a smaller calibration resistance to benefit from increased memory and speed.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: June 1, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ankur Agrawal, Simarpreet Kaur
  • Publication number: 20210150803
    Abstract: Methods and apparatus to transition between 2D and 3D renderings of augmented reality content are disclosed. An example apparatus includes at least one processor to execute instructions to: determine a first intended movement of an augmented reality (AR) object projected onto a first surface in a real world environment; cause the AR object to be rendered to appear to move along the first surface at a fixed depth defined by the first surface; determine a second intended movement of the AR object projected onto a second surface in the real world environment; and cause the AR object to be rendered to appear to move with variable depth within a 3D virtual space, the 3D virtual space defined by the second surface and a virtual rear boundary, the virtual rear boundary to virtually extend behind the second surface from a perspective of a user.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 20, 2021
    Inventors: Pete Denman, John Sherry, Glen J. Anderson, Benjamin Bair, Rebecca Chierichetti, Ankur Agrawal, Meng Shi
  • Publication number: 20210109709
    Abstract: In an embodiment, a method includes configuring a specialized circuit for floating point computations using numbers represented by a hybrid format, wherein the hybrid format includes a first format and a second format. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a numeric value in the first format during a forward pass for training a deep learning network. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a second numeric value in the second format during a backward pass for training the deep learning network.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: International Business Machines Corporation
    Inventors: Naigang Wang, Jungwook Choi, Kailash Gopalakrishnan, Ankur Agrawal, Silvia Melitta Mueller
  • Patent number: 10970937
    Abstract: Technologies for virtual attribute assignment include a compute device. The compute device is configured to receive an attribute assignment command from a user and analyze the attribute assignment command to determine a user-selected virtual object, a user-referenced attribute of the user-selected virtual object, a user-selected real object, and a user-referenced attribute of the user-selected real object. Based on the attribute assignment command, the compute device is further configured to determine a state of the user-referenced attribute of the user-selected real object and update a state of the user-referenced attribute of the user-selected virtual object based on the state of the user-referenced attribute of the user-selected real object.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Glen J. Anderson, Carl Marshall, John Sherry, Rebecca Chierichetti, Ankur Agrawal, Meng Shi, Giuseppe Raffa
  • Patent number: 10963219
    Abstract: In an embodiment, a method includes configuring a specialized circuit for floating point computations using numbers represented by a hybrid format, wherein the hybrid format includes a first format and a second format. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a numeric value in the first format during a forward pass for training a deep learning network. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a second numeric value in the second format during a backward pass for training the deep learning network.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: March 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naigang Wang, Jungwook Choi, Kailash Gopalakrishnan, Ankur Agrawal, Silvia Melitta Mueller
  • Publication number: 20210074866
    Abstract: Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment the optoelectronic system comprises a board, and a carrier attached to the board. In an embodiment, a first die is on the carrier. In an embodiment, the first die is a photonics die, and a surface of the first die is covered by an optically transparent layer.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Inventors: Priyanka DOBRIYAL, Ankur AGRAWAL, Susheel JADHAV, Quan TRAN, Raghuram NARAYAN, Raiyomand ASPANDIAR, Kenneth BROWN, John HECK
  • Publication number: 20210066882
    Abstract: An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Applicant: INTEL CORPORATION
    Inventors: Priyanka Dobriyal, Susheel G. Jadhav, Ankur Agrawal, Quan A. Tran, Raiyomand F. Aspandiar, Kenneth M. Brown
  • Patent number: 10909751
    Abstract: Methods and apparatus to transition between 2D and 3D renderings of augmented reality content are disclosed. An example apparatus includes a user input analyzer to determine an intended movement of an AR object relative to a first zone of a real world environment and a second zone of the real world environment. The apparatus also includes an AR content generator, in response to user input, to: render an appearance of movement of the AR object in the first zone based upon a first set of rules; and render the AR object in the second zone, movement of the AR object in the second zone based on a second set of rules different than the first set of rules.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: February 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Pete Denman, John Sherry, Glen J. Anderson, Benjamin Bair, Rebecca Chierichetti, Ankur Agrawal, Meng Shi
  • Publication number: 20210019116
    Abstract: A computer-implemented method for performing an exponential calculation using only two fully-pipelined instructions in a floating point unit that includes. The method includes computing an intermediate value y? by multiplying an input operand with a predetermined constant value. The input operand is received in floating point representation. The method further includes computing an exponential result for the input operand by executing a fused instruction. The fused instructions includes converting the intermediate value y? to an integer representation z represented by v most significant bits (MSB), and w least significant bits (LSB). The fused instruction further includes determining exponent bits of the exponential result based on the v MSB from the integer representation z. The method further includes determining mantissa bits of the exponential result according to a piece-wise linear mapping function using a predetermined number of segments based on the w LSB from the integer representation z.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Xiao Sun, Ankur Agrawal, Kailash Gopalakrishnan, Silvia Melitta Mueller, Kerstin Claudia Schelm
  • Publication number: 20210004294
    Abstract: A method and system are provided for handling a blockchain network based file storage system including a plurality of electronic devices.
    Type: Application
    Filed: February 11, 2020
    Publication date: January 7, 2021
    Inventors: Vipul GUPTA, Ankur Agrawal, Rahul Agrawal, Prashant Sharma, Kalgesh Singh, Saurabh Kumar, Anil Kumar Saini
  • Publication number: 20200401413
    Abstract: Various embodiments are provided for using a reduced precision based programmable and single instruction multiple data (SIMD) dataflow architecture in a computing environment. One or more instructions between a plurality of execution units (EUs) operating in parallel within each one of a plurality of execution elements (EEs).
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kailash GOPALAKRISHNAN, Sunil SHUKLA, Jungwook CHOI, Silvia MUELLER, Bruce FLEISCHER, Vijayalakshmi SRINIVASAN, Ankur AGRAWAL, Jinwook OH
  • Publication number: 20200387351
    Abstract: Embodiments for implementing a fused multiply-multiply-accumulate (“FMMA”) unit by one or more processors in a computing system. Mantissas for two products, an exponent difference of the two products serving as an alignment shift amount for a product of the two products having a smallest exponent, and an alignment shift amount for an addend relative to an alternative product of the two product having a larger exponent may be determined in parallel. The addend may be aligned relative to the alternative product having the larger exponent. The product having the smallest exponent may be aligned relative to the alternative product having the larger exponent according to the alignment shift amount.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 10, 2020
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ankur AGRAWAL, Silvia MUELLER, Kailash GOPALAKRISHNAN, Bruce FLEISCHER, Balaram SINHAROY, Mingu KANG
  • Publication number: 20200310755
    Abstract: Techniques facilitating binary floating-point multiply and scale operation for compute-intensive numerical applications and apparatuses are provided. An embodiment relates to a system that can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a receiver component that receives an instruction to perform a multiply and scale operation of the first floating point operand value, the second floating point operand value, and the integer operand value, wherein the multiplication component obtains the floating-point product in response to the instruction to perform the multiply and scale operation. The multiplication can be performed as a single instruction.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Silvia Melitta Mueller, Bruce Fleischer, Ankur Agrawal, Kailash Gopalakrishnan
  • Publication number: 20200302301
    Abstract: Logic may determine a specific performance of a neural network based on an event and may present the specific performance to provide a user with an explanation of the inference by a machine learning model such as a neural network. Logic may determine a first activation profile associated with the event, the first activation profile based on activation of nodes in one or more layers of the neural network during inference to generate an output. Logic may correlate the first activation profile against a second activation profile associated with a first training sample of training data. Logic may determine that the first training sample is associated with the event based on the correlation. Logic may output an indicator to identify the first training sample as being associated with the event.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Glen J. Anderson, Rajesh Poornachandran, Ignacio Alvarez, Giuseppe Raffa, Jill Boyce, Ankur Agrawal, Kshitij Doshi
  • Publication number: 20200304574
    Abstract: A method of storing or searching data files on a plurality of cloud-based storage systems includes detecting an event on the electronic device indicative of storing at least one data file on a cloud-based storage, analyzing the at least one data file in response to detecting the event to extract a plurality of elements, mapping the plurality of elements to one or more rules stored in a memory of the electronic device, selecting at least one cloud-based storage for storing the at least one data file, and storing information corresponding to the at least one data file in the memory upon storing the at least one data file onto the selected at least one cloud-based storage for searching the at least one data file.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 24, 2020
    Inventors: Vipul Gupta, Ankur Agrawal, Rahul Agrawal, Prashant Sharma, Anil Kumar Saini, Kalgesh Singh, Saurabh Kumar
  • Publication number: 20200249910
    Abstract: In an embodiment, a method includes configuring a specialized circuit for floating point computations using numbers represented by a hybrid format, wherein the hybrid format includes a first format and a second format. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a numeric value in the first format during a forward pass for training a deep learning network. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a second numeric value in the second format during a backward pass for training the deep learning network.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Applicant: International Business Machines Corporation
    Inventors: NAIGANG WANG, Jungwook Choi, Kailash Gopalakrishnan, Ankur Agrawal, Silvia Melitta Mueller
  • Publication number: 20200233642
    Abstract: Techniques for operating on and calculating binary floating-point numbers using an enhanced floating-point number format are presented. The enhanced format can comprise a single sign bit, six bits for the exponent, and nine bits for the fraction. Using six bits for the exponent can provide an enhanced exponent range that facilitates desirably fast convergence of computing-intensive algorithms and low error rates for computing-intensive applications. The enhanced format can employ a specified definition for the lowest binade that enables the lowest binade to be used for zero and normal numbers; and a specified definition for the highest binade that enables it to be structured to have one data point used for a merged Not-a-Number (NaN)/infinity symbol and remaining data points used for finite numbers. The signs of zero and merged NaN/infinity can be “don't care” terms. The enhanced format employs only one rounding mode, which is for rounding toward nearest up.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 23, 2020
    Inventors: Silvia Melitta Mueller, Ankur Agrawal, Bruce Fleischer, Kailash Gopalakrishnan, Dongsoo Lee
  • Patent number: 10656913
    Abstract: Techniques for operating on and calculating binary floating-point numbers using an enhanced floating-point number format are presented. The enhanced format can comprise a single sign bit, six bits for the exponent, and nine bits for the fraction. Using six bits for the exponent can provide an enhanced exponent range that facilitates desirably fast convergence of computing-intensive algorithms and low error rates for computing-intensive applications. The enhanced format can employ a specified definition for the lowest binade that enables the lowest binade to be used for zero and normal numbers; and a specified definition for the highest binade that enables it to be structured to have one data point used for a merged Not-a-Number (NaN)/infinity symbol and remaining data points used for finite numbers. The signs of zero and merged NaN/infinity can be “don't care” terms. The enhanced format employs only one rounding mode, which is for rounding toward nearest up.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Silvia Melitta Mueller, Ankur Agrawal, Bruce Fleischer, Kailash Gopalakrishnan, Dongsoo Lee
  • Patent number: 10593119
    Abstract: The present disclosure is directed to systems, apparatuses, and processes that provide mixed reality and/or augmented reality interactive environments. Disclosed embodiments include mechanisms to determine a location of a physical object within a mixed reality environment, determine a location of a viewer within the mixed reality environment, and project a display onto the physical object or on a portion of an area within the mixed reality environment proximate to the physical object to obscure the physical object from the viewer, based upon at least the location of the physical object with respect to the location of the viewer. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Glen J. Anderson, Carl Marshall, Ankur Agrawal, Meng Shi, Selvakumar Panneer