Abstract: Embodiments for implementing a fused multiply-multiply-accumulate (“FMMA”) unit by one or more processors in a computing system. Mantissas for two products, an exponent difference of the two products serving as an alignment shift amount for a product of the two products having a smallest exponent, and an alignment shift amount for an addend relative to an alternative product of the two product having a larger exponent may be determined in parallel. The addend may be aligned relative to the alternative product having the larger exponent. The product having the smallest exponent may be aligned relative to the alternative product having the larger exponent according to the alignment shift amount.

Abstract: Language education systems capable of integrating with a user's daily life and automatically producing educational prompts would be particularly advantageous. An example method includes determining a user's identity, detecting a language education subject, prompting the user with a language education message, receiving a user's response, and updating a user profile associated with the user based on the user's response. Methods may also include determining user state (including emotional, physical, social, etc.) and determining, based on the user state, whether to prompt the user with the language education prompt.

Abstract: Methods and apparatus to transition between 2D and 3D renderings of augmented reality content are disclosed. An example apparatus includes at least one processor to execute instructions to: determine a first intended movement of an augmented reality (AR) object projected onto a first surface in a real world environment; cause the AR object to be rendered to appear to move along the first surface at a fixed depth defined by the first surface; determine a second intended movement of the AR object projected onto a second surface in the real world environment; and cause the AR object to be rendered to appear to move with variable depth within a 3D virtual space, the 3D virtual space defined by the second surface and a virtual rear boundary, the virtual rear boundary to virtually extend behind the second surface from a perspective of a user.

Abstract: A system, method and processor readable medium for identifying an operational design domain (ODD) for operation of an autonomous driving system (ADS). In one aspect, a proposed map is used to generate a geographic dataset. Performance of the ADS is evaluated against the geographic dataset under a range of environment& conditions, thereby identifying a bounded-risk portion of a proposed condition space defined by the proposed map and the range of environmental conditions. The operational design domain is identified based on the bounded-risk portion of the proposed condition space. The ODD can be updated as additional data is received. When a vehicle using the ADS is likely to leave the ODD, an operator can be alerted.

Abstract: A method and system are provided for handling a blockchain network based file storage system including a plurality of electronic devices.

Abstract: A method for preventing data leakage may include: identifying data that is generated by at least one framework application in response to a data request from a first machine learning (ML) engine of a plurality of ML engines; creating a plurality of data blocks based on the generated data, a category of the first ML engine, and a tag associated with the first ML engine and the at least one framework application; determining whether the plurality of data blocks are valid to share with the first ML engine using an activity block chain associated with each of the plurality of framework applications; based on the plurality of data blocks being valid, sharing the plurality of data blocks with the first ML engine, and otherwise discarding the plurality of data blocks not to share with the first ML engine.

Abstract: An apparatus includes a floating-point gradient register; an integer register; a memory bank; and an array of processing units. Each of the units includes a plurality of binary shifters having an integer input configured to obtain corresponding bits of a 4-bit integer multiplicand, and a shift-specifying input configured to obtain corresponding bits in an exponent field of a 4-bit floating point multiplier. The multiplier is specified in a mantissaless four-bit floating point format including a sign bit, three exponent bits, and no mantissa bits. An adder tree has a plurality of inputs coupled to outputs of the plurality of shifters, and a rounder has an input coupled to an output of the adder tree. The integer inputs are connected to the integer register; the shift-specifying inputs are connected to the floating-point gradient register; and outputs of the rounders are coupled to the memory bank.

Abstract: A reduced precision based programmable and single instruction multiple data (SIMD) dataflow architecture includes reduced precision execution units with a majority of the execution units operating at reduced precision and a minority of the execution units are capable of operating at higher precision. The execution units operate in parallel within a programmable execution element to share instruction fetch, decode, and issue pipelines and operate on the same instruction in lock-step to minimize instruction-related overhead.

Abstract: Aspects of a storage device including a controller, a calibration resistor and a die having an output driver and a calibration circuit are provided, which allow for an output impedance of the output driver to be calibrated to a lower impedance than a minimum required for reading data across PVT variations of the die at maximum loading of the controller. To check whether slow corners may operate using the lower impedance, the controller determines whether the output impedance of the output driver can be calibrated to the lower impedance at a maximum temperature and minimum voltage applied to the die, or whether a calibration code generated from the calibration circuit exceeds a threshold at a nominal temperature and voltage applied to the die. Thus, slow corners are screened out from lower impedance use, while faster devices are designed with a smaller calibration resistance to benefit from increased memory and speed.

Abstract: Embodiments of the present invention provide a computer-implemented method for adaptive residual gradient compression for training of a deep learning neural network (DNN). The method includes obtaining, by a first learner, a current gradient vector for a neural network layer of the DNN, in which the current gradient vector includes gradient weights of parameters of the neural network layer that are calculated from a mini-batch of training data. A current residue vector is generated that includes residual gradient weights for the mini-batch. A compressed current residue vector is generated based on dividing the residual gradient weights of the current residue vector into a plurality of bins of a uniform size and quantizing a subset of the residual gradient weights of one or more bins of the plurality of bins. The compressed current residue vector is then transmitted to a second learner of the plurality of learners or to a parameter server.

Abstract: Various embodiments are provided for performing hybrid precision floating point format computation via a simplified superset floating point unit in a computing system. One or more inputs, represented as a plurality of floating point number formats, may be converted into a superset floating point format prior to computation by one or more simplified superset floating point units (ssFPUs). A compute operation may be performed on the one or more inputs represented as the superset floating point format using the one or more ssFPUs.

Abstract: A multiply-accumulate device comprises a digital multiplication circuit and a mixed signal adder. The digital multiplication circuit is configured to input L m1-bit multipliers and L m2-bit multiplicands and configured to generate N one-bit multiplication outputs, each one-bit multiplication output corresponding to a result of a multiplication of one bit of one of the L m1-bit multipliers and one bit of one of the L m2-bit multiplicands. The mixed signal adder comprises one or more stages, at least one stage configured to input the N one-bit multiplication outputs, each stage comprising one or more inner product summation circuits; and a digital reduction stage coupled to an output of a last stage of the one or more stages and configured to generate an output of the multiply-accumulate device based on the L m1-bit multipliers and the L m2-bit multiplicands.

Abstract: Techniques facilitating binary floating-point multiply and scale operation for compute-intensive numerical applications and apparatuses are provided. An embodiment relates to a system that can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a receiver component that receives an instruction to perform a multiply and scale operation of the first floating point operand value, the second floating point operand value, and the integer operand value, wherein the multiplication component obtains the floating-point product in response to the instruction to perform the multiply and scale operation. The multiplication can be performed as a single instruction.

Abstract: A computer-implemented method for performing an exponential calculation using only two fully-pipelined instructions in a floating point unit that includes. The method includes computing an intermediate value y? by multiplying an input operand with a predetermined constant value. The input operand is received in floating point representation. The method further includes computing an exponential result for the input operand by executing a fused instruction. The fused instructions includes converting the intermediate value y? to an integer representation z represented by v most significant bits (MSB), and w least significant bits (LSB). The fused instruction further includes determining exponent bits of the exponential result based on the v MSB from the integer representation z. The method further includes determining mantissa bits of the exponential result according to a piece-wise linear mapping function using a predetermined number of segments based on the w LSB from the integer representation z.

Abstract: Aspects of a storage device including a controller, a calibration resistor and a die having an output driver and a calibration circuit are provided, which allow for an output impedance of the output driver to be calibrated to a lower impedance than a minimum required for reading data across PVT variations of the die at maximum loading of the controller. To check whether slow corners may operate using the lower impedance, the controller determines whether the output impedance of the output driver can be calibrated to the lower impedance at a maximum temperature and minimum voltage applied to the die, or whether a calibration code generated from the calibration circuit exceeds a threshold at a nominal temperature and voltage applied to the die. Thus, slow corners are screened out from lower impedance use, while faster devices are designed with a smaller calibration resistance to benefit from increased memory and speed.

Abstract: Provided is a method, performed by an electronic device, of performing an operation based on bending, the method including: sensing bending that deforms a shape of the electronic device; determining a first region, from which the bending is sensed, from among regions of the electronic device; selecting an object indicated by the first region from at least one object displayed on the electronic device; and performing an operation on the selected object.

Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data, wherein the sensor data is captured by a plurality of sensors within an educational environment. The processor is to: access the sensor data captured by the plurality of sensors; identify a student within the educational environment based on the sensor data; detect a plurality of events associated with the student based on the sensor data, wherein each event is indicative of an attention level of the student within the educational environment; generate a report based on the plurality of events associated with the student; and send the report to a third party associated with the student.

Abstract: Methods and apparatus for projecting augmented reality (AR) enhancements to real objects in response to user gestures detected in a real environment are disclosed. An example apparatus includes one or more processors to execute computer-readable instructions to identify a user gesture within a real environment based on data obtained from a motion sensor. The user gesture is associated with a target real object from among one or more real objects located within the real environment. The user gesture represents a desired shape of a desired virtual drawing to be projected to the target real object. The one or more processors are further to execute the instructions to determine an AR enhancement based on the user gesture and the target real object. The AR enhancement includes a virtual drawing having a shape corresponding to the desired shape of the desired virtual drawing.

Abstract: A system, method and processor readable medium for identifying an operational design domain (ODD) for operation of an autonomous driving system (ADS). In one aspect, a proposed map is used to generate a geographic dataset. Performance of the ADS is evaluated against the geographic dataset under a range of environment& conditions, thereby identifying a bounded-risk portion of a proposed condition space defined by the proposed map and the range of environmental conditions. The operational design domain is identified based on the bounded-risk portion of the proposed condition space. The ODD can be updated as additional data is received. When a vehicle using the ADS is likely to leave the ODD, an operator can be alerted.

Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonic engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonic engines are communicatively coupled to the die through the first package substrate and the second package substrate.