Patents by Inventor Anthony J. Lochtefeld

Anthony J. Lochtefeld has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9601623
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • Publication number: 20170077330
    Abstract: Structures including crystalline material disposed in openings defined in a non-crystalline mask layer disposed over a substrate. A photovoltaic cell may be disposed above the crystalline material.
    Type: Application
    Filed: November 23, 2016
    Publication date: March 16, 2017
    Inventors: Jizhong Li, Anthony J. Lochtefeld, Calvin Sheen, Zhiyuan Cheng
  • Patent number: 9576951
    Abstract: Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9548236
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: January 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 9543472
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9508724
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mayank T. Bulsara, Anthony J. Lochtefeld, Matthew T. Currie
  • Patent number: 9508890
    Abstract: Structures including crystalline material disposed in openings defined in a non-crystalline mask layer disposed over a substrate. A photovoltaic cell may be disposed above the crystalline material.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jizhong Li, Anthony J. Lochtefeld, Calvin Sheen, Zhiyuan Cheng
  • Patent number: 9484434
    Abstract: Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: James Fiorenza, Mark Carroll, Anthony J. Lochtefeld
  • Patent number: 9455299
    Abstract: Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: September 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiyuan Cheng, James Fiorenza, Calvin Sheen, Anthony J. Lochtefeld
  • Patent number: 9449868
    Abstract: A method of forming a photonic device that comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The method may further include forming a top diode material and an active diode region between the top and bottom diode materials.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacutring Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9431243
    Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Matthew T. Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas A. Langdo
  • Publication number: 20160218173
    Abstract: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 28, 2016
    Inventors: Jie Bai, Anthony J. Lochtefeld, Ji-Soo Park
  • Publication number: 20160211260
    Abstract: Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventor: Anthony J. Lochtefeld
  • Publication number: 20160190254
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Publication number: 20160133787
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Application
    Filed: December 29, 2015
    Publication date: May 12, 2016
    Inventor: Anthony J. Lochtefeld
  • Publication number: 20160111285
    Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Inventors: Anthony J. Lochtefeld, Matthew T. Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas A. Langdo
  • Patent number: 9318325
    Abstract: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Bai, Anthony J. Lochtefeld, Ji-Soo Park
  • Patent number: 9299562
    Abstract: Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9281376
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Publication number: 20160064492
    Abstract: A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.
    Type: Application
    Filed: September 3, 2015
    Publication date: March 3, 2016
    Inventors: Jizhong Li, Anthony J. Lochtefeld