Patents by Inventor Arthur Wang
Arthur Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240129605Abstract: Provided are methods for cascade camera image signal processing (ISP) tuning, which can include receiving first image data at a first time associated with a first image sensor of a camera, generating at least one tuned first ISP block parameter for at least one first ISP block based on the first image data and first tuning criterion, receiving second image data at a second time, and generating at least one tuned second ISP block parameter for at least one second ISP block based on the second image data and second tuning criterion. Some methods described also include tuning parameters of at least one ISP block of a camera after receiving tuned parameters. Some methods describe also include generating an image using ISP blocks tuned using various tuning criteria. Systems and computer program products are also provided.Type: ApplicationFiled: February 6, 2023Publication date: April 18, 2024Inventors: Lin Luo, Arthur Safira, Jeongil Ju, Ting Wang
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Publication number: 20240123944Abstract: Provided are devices for camera cleaning and flare reduction for vehicles, which can include a cleaning device for cleaning a transparent window of a housing containing a camera system. The devices can include optical panels with different properties that can be moved in front of the transparent window for flare reduction. Methods are provided which can include analyzing at least one image to determine a presence of an optical flare within the at least one image, and, based on detecting the optical flare, causing at least one optical panel to be moved into a position in front of a lens of the imaging device. Computer program products are also provided.Type: ApplicationFiled: December 29, 2022Publication date: April 18, 2024Inventors: Lin Luo, Arthur Safira, Ting Wang
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Patent number: 11962475Abstract: The properties of a plurality of operational units are estimated by generating a central system state graph model representing the properties of the plurality of operational units as probabilities of transitions between states for the plurality of operational units, where the states represent operational data. Then a respective updated system state graph model is generated for each of the plurality of operational units, based on the central system state graph model and based on new operational data for the respective operational unit. A distance measure is determined between the respective updated system state graph models. If the distance measure fulfils a divergence criterion, a plurality of new central system state graph models are generated, each representing the properties of a respective subset of the plurality of operational units as the probabilities of transitions between states for the respective subset of the plurality of operational units.Type: GrantFiled: February 3, 2020Date of Patent: April 16, 2024Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Martha Vlachou-Konchylaki, Efthymios Stathakis, Arthur Gusmao, Jörg Niemöller, Swarup Kumar Mohalik, Yu Wang
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Patent number: 11951133Abstract: Compounds, compositions, and methods for use in inhibiting the E3 enzyme Cbl-b in the ubiquitin proteasome pathway are disclosed. The compounds, compositions, and methods can be used to modulate the immune system, to treat diseases amenable to immune system modulation, and for treatment of cells in vivo, in vitro, or ex vivo. Also disclosed are pharmaceutical compositions comprising a Cbl-b inhibitor and a cancer vaccine, as well as methods for treating cancer using a Cbl-b inhibitor and a cancer vaccine; and pharmaceutical compositions comprising a Cbl-b inhibitor and an oncolytic virus, as well as methods for treating cancer using a Cbl-b inhibitor and an oncolytic virus.Type: GrantFiled: July 13, 2022Date of Patent: April 9, 2024Assignee: NURIX THERAPEUTICS, INC.Inventors: Arthur T. Sands, Neil F. Bence, Christoph W. Zapf, Frederick Cohen, Chenbo Wang, Thomas Cummins, Hiroko Tanaka, Hunter Shunatona, Mario Cardozo, Dahlia Weiss, Jennifa Gosling
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Publication number: 20240088066Abstract: A semiconductor wafer (1a, 1b) including a plurality of chips (2) and a separation zone (3) spacing the semiconductor chips (2) from each other in this wafer (1a, 1b), such a separation zone (3) extending from a front face (4a) to an opposite backside face (4b) of this wafer (1a, 1b), this separation zone (3) includes a scribe line (6) configured to be diced using plasma etching and an inlet area (13) of this scribe line (6), the inlet (13) being delimitated by free ends of plasma etch-resistant material layers (9) extending each from a peripheral wall (20) of a functional part (18) of a chip (2) into the scribe line (6) by overlapping a top of a seal ring (7) of this chip (2).Type: ApplicationFiled: September 8, 2023Publication date: March 14, 2024Applicant: EM Microelectronic-Marin SAInventors: Christophe ENTRINGER, Yves Dupraz, Pierre Muller, Zeng Wang, Alexis Durand, Arthur Hugh MacDougall
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Publication number: 20240078961Abstract: Systems and methods are described herein to control brightness based on image content or other inputs to a display system. A dual-control system may integrate both slow control operations and fast control operations into a cohesive brightness management system. By using both shorter-term (e.g., fast control) and longer-term (e.g., slow control) brightness adjustment operations, the electronic device may quickly respond to high luminance and high brightness situations that may cause burn-in into the display, image artifacts, or other damage. Responding quickly to these high consumption situations may prevent damage or perceivable upset to an ongoing process, among other benefits.Type: ApplicationFiled: December 6, 2022Publication date: March 7, 2024Inventors: Wanqing Xin, Yang Xu, Mohammad Ali Jangda, Jenny Hu, Koorosh Aflatooni, Giovanni Corradini, Martin Kocicka, Alexey Kornienko, Asha G Karvaje, Aishwarya Prem Renu, Andrew D Pangborn, Chaohao Wang, Yingying Tang, Arthur L Spence, Mahesh B Chappalli
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Patent number: 11616145Abstract: A method of forming a FinFET stack gate memory includes a nitride film forming step, a nitride film is formed on a memory cell area with a shallow trench isolation (STI) structure; a stripping step, a portion of the nitride film is stripped, the other portion of the nitride film is remained at the STI structure, and a STI oxide is disposed in the STI structure; a floating gate (FG) structure forming step, a tunnel oxide is disposed, and a first polysilicon is disposed to form a FG structure; an oxide-nitride-oxide (ONO) layer disposing step, a portion of the STI oxide is stripped, and an ONO layer is disposed; a removing step, a portion of the ONO layer is removed; a control gate (CG) structure forming step, a portion of the FG structure is removed, and a second polysilicon is disposed to form a CG structure.Type: GrantFiled: December 28, 2021Date of Patent: March 28, 2023Assignee: INTEGRATED SILICON SOLUTION INC.Inventor: Hsingya Arthur Wang
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Publication number: 20220123146Abstract: A method of forming a FinFET stack gate memory includes a nitride film forming step, a nitride film is formed on a memory cell area with a shallow trench isolation (STI) structure; a stripping step, a portion of the nitride film is stripped, the other portion of the nitride film is remained at the STI structure, and a STI oxide is disposed in the STI structure; a floating gate (FG) structure forming step, a tunnel oxide is disposed, and a first polysilicon is disposed to form a FG structure; an oxide-nitride-oxide (ONO) layer disposing step, a portion of the STI oxide is stripped, and an ONO layer is disposed; a removing step, a portion of the ONO layer is removed; a control gate (CG) structure forming step, a portion of the FG structure is removed, and a second polysilicon is disposed to form a CG structure.Type: ApplicationFiled: December 28, 2021Publication date: April 21, 2022Inventor: Hsingya Arthur WANG
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Publication number: 20220020721Abstract: A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step. In the wafer-bonding step, at least two wafers are corresponding to and bonded to each other by bonding surfaces thereof. In the TSV forming step, a TSV structure is formed on at least one side of a seal ring structure of one of the wafers, a conductive filler is disposed in the TSV structure, and the TSV structure is overlapped the side of one of the seal ring structure of one of the wafers and a portion of a seal ring structure of another one of the wafers. In the forming bonding pad step, a bonding pad is formed on an outer surface which is relative to the bonding surface of the wafer with the TSV structure, so as to form the wafer-bonding structure.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Inventors: Hsingya Arthur WANG, Sheng-Yuan CHOU, Yu-Ting WANG, Wan-Yi CHANG
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Publication number: 20210296281Abstract: A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step. In the wafer-bonding step, at least two wafers are corresponding to and bonded to each other by bonding surfaces thereof. In the TSV forming step, a TSV structure is formed on at least one side of a seal ring structure of one of the wafers, a conductive filler is disposed in the TSV structure, and the TSV structure is overlapped the side of one of the seal ring structure of one of the wafers and a portion of a seal ring structure of another one of the wafers. In the forming bonding pad step, a bonding pad is formed on an outer surface which is relative to the bonding surface of the wafer with the TSV structure, so as to form the wafer-bonding structure.Type: ApplicationFiled: March 20, 2020Publication date: September 23, 2021Inventors: Hsingya Arthur WANG, Sheng-Yuan CHOU, Yu-Ting WANG, Wan-Yi CHANG
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Publication number: 20210143275Abstract: A method of forming a FinFET stack gate memory includes a nitride film forming step, a nitride film is formed on a memory cell area with a shallow trench isolation (STI) structure; a stripping step, a portion of the nitride film is stripped, the other portion of the nitride film is remained at the STI structure, and a STI oxide is disposed in the STI structure; a floating gate (FG) structure forming step, a tunnel oxide is disposed, and a first polysilicon is disposed to form a FG structure; an oxide-nitride-oxide (ONO) layer disposing step, a portion of the STI oxide is stripped, and an ONO layer is disposed; a removing step, a portion of the ONO layer is removed; a control gate (CG) structure forming step, a portion of the FG structure is removed, and a second polysilicon is disposed to form a CG structure.Type: ApplicationFiled: March 11, 2020Publication date: May 13, 2021Inventor: Hsingya Arthur WANG
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Publication number: 20180289548Abstract: Goggles with a ventilation structure have a frame, a lens, and a strap. The frame has multiple ventilation portions formed on an inner peripheral surface of the frame. The lens is mounted on the frame and has multiple through holes disposed along a peripheral edge of the lens and respectively communicating with the ventilation portions. The strap has two ends respectively connected to two opposite sides of the frame. Air outside the goggles can ventilate a space defined between the lens and a face of a wearer via the ventilation portions and the through holes, so as to dissipate heat accumulated in the space and to prevent the lens from fogging. Formation of the ventilation portions and the through holes does not require expanding a shape of the frame of the goggles. Thus, the goggles have compact volume and light weight and are comfortable for wearing.Type: ApplicationFiled: April 6, 2017Publication date: October 11, 2018Inventor: Arthur Wang
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Publication number: 20170354538Abstract: Provided is an eyewear component with a replaceable lens, comprising a lens, a first buckle and a second buckle. The lens has a first end and a second end, the first end has an opening, and the second end has an elongated hole and a notch; the first buckle has a fixed element detachably received in the opening of the first end, and the fixed element has a head portion and a neck portion; the second buckle has an upper buckled portion and a lower buckled portion, the upper buckled portion and the lower buckled portion are detachably received in the elongated hole and the notch respectively. Therefore, the lens is not only easy to be buckled to the first buckle and the second buckle, but also easy to be detached for changing the lens.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Inventor: ARTHUR WANG
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Publication number: 20170103813Abstract: Disclosed is an effective programming method for non-volatile flash memory including memory cells, each formed of a select transistor and a floating transistor. The method includes imposing a positive voltage onto a control gate of the floating transistor as a word line, supplying a zero voltage to a triple well, a deep N well, and a select gate of the select transistor to turn off the select transistor, and finally providing a moderate positive voltage to a drain of the control transistor. Owing to the junction band-to-band tunneling effect, the electron of the hole-electron pair generated between the junction of the bit line and the triple well leaps to the floating gate of the floating transistor driven by the positive electric field to form a higher threshold voltage for the memory cell such that the process of programming is accomplished.Type: ApplicationFiled: November 25, 2015Publication date: April 13, 2017Inventors: Arthur Wang, Sam Chou, Jyh-Kuang Lin
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Patent number: 9360685Abstract: An eyeglasses clip device for climbing has a body, two lens heads, and a pressing clamp. The body has a nose groove, two windows, two mounting recesses, and four guiding bars. The windows are formed through the body. The mounting recesses are formed in a front side of the body and are respectively formed around the windows. The guiding bars are forwardly formed on and protrude from the front side of the body respectively beside the mounting recesses. The lens heads are movably connected to the body respectively in the mounting recesses, and each one of the lens heads has an outer casing, a first lens, a second lens, and a mirror. The pressing clamp is detachably connected to the body between the lens heads and has a fixed frame and a pressing frame.Type: GrantFiled: April 6, 2015Date of Patent: June 7, 2016Inventor: Arthur Wang
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Publication number: 20150097986Abstract: An itinerary generation apparatus, method, and non-transitory computer readable storage medium thereof are provided. The itinerary generation apparatus includes a storage unit, an interface, and a processing unit, wherein the processing unit is electrically connected to the storage unit and the interface. The storage unit is stored with a piece of information related to a place. The interface is configured to receive a plurality of images, wherein each of the images has a shoot time. The processing unit determines that a portion of the images corresponds to the place according to a piece of schedule information. The processing unit retrieves the piece of information related to the place from the storage unit after determining that the portion corresponds to the place.Type: ApplicationFiled: November 21, 2013Publication date: April 9, 2015Applicant: Institute For Information IndustryInventors: Zonyin SHAE, Ko-Yang WANG, Grace LIN, Arthur WANG, Ting-Chieh TU, Ya-Hui CHAN, Meng-Jung SHIH, Ping-I CHEN, Tai-Chun WANG
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Patent number: 8946003Abstract: A semiconductor transistor is formed as follows. A gate electrode is formed over but is insulated from a semiconductor body region. A first layer of insulating material is formed over the gate electrode and the semiconductor body region. A second layer of insulating material different from the first layer of insulating material is formed over the first layer of insulating material. Only the second layer of insulating material is etched to form spacers along the side-walls of the gate electrode. Impurities are implanted through the first layer of insulating material to form a source region and a drain region in the body region. A substantial portion of those portions of the first layer of insulting material extending over the source and drain regions is removed.Type: GrantFiled: February 20, 2007Date of Patent: February 3, 2015Assignee: SK hynix Inc.Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Patent number: 8288219Abstract: A stack of two polysilicon layers is formed over a semiconductor body region. A DDD implant is performed to form a DDD source region in the semiconductor body region along a source side of the polysilicon stack but not along a drain side of the polysilicon stack. Off-set spacers are formed along opposing side-walls of the polysilicon stack. A source/drain implant is performed to form a drain region in the semiconductor body region along the drain side of the polysilicon stack and to form a highly doped region within the DDD source region such that the extent of an overlap between the polysilicon stack and each of the drain region and the highly doped region is inversely dependent on a thickness of the off-set spacers, and a lateral spacing directly under the polysilicon stack between adjacent edges of the DDD source region and the highly doped region is directly dependent on the thickness of the off-set spacers.Type: GrantFiled: March 20, 2008Date of Patent: October 16, 2012Assignee: Hynix Semiconductor, Inc.Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Publication number: 20120137817Abstract: A power control member for manned vehicles is revealed. The power control member includes a handle, a stem support and a power controller. The handle is sleeved and assembled with the stem support of a manned vehicle, and the power controller is arranged between the handle and the stem support. A power control shaft of the power controller shares the same axis with the handle and connects to the handle. Thereby rotation of the handle drives the power controller to control the direction and speed of the manned vehicle.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Applicant: FREERIDER CORP.Inventor: ARTHUR WANG
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Patent number: 8038165Abstract: A foldable wheeled vehicle for individuals includes a main body, front and rear wheels joined on the body, and an anti-tip wheel joined on a rear end of the main vehicle body; the rear wheels will be in an immobilized state when the vehicle isn't in-use; the anti-tilting wheel will move to be below the rear wheels automatically when the vehicle is folded; thus, the vehicle in the folded position can be dragged with the front wheels and the anti-tip wheel contacting the ground; secondly, the anti-tip wheel will be in a higher position than the rear wheels when the vehicle is in an expanded in-use position; thus, when the vehicle is moving along a slope and tilting rearwards, the anti-tip wheel will contact the ground to prevent the vehicle from tilting rearwards excessively to overturn.Type: GrantFiled: October 8, 2008Date of Patent: October 18, 2011Inventor: Arthur Wang