Abstract: A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.

Abstract: A gate electrode is formed over but is insulated from a semiconductor body region for each of first and second transistors. Off-set spacers are formed along side-walls of the gate electrode of each of the first and second transistors. After forming the off-set spacers, a DDD implant is performed to form DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, main spacers are formed adjacent the off-set spacers of at least the first transistor. A LDD implant is performed to form LDD source and LDD drain regions for the second transistor. After forming the main spacers, a source/drain (S/D) implant is carried out to form a highly doped region within each of the DDD drain and DDD source regions and each of the LDD drain and LDD source regions.

Abstract: In accordance with an embodiment of the present invention, a semiconductor structure includes an undoped polysilicon layer, a doped polysilicon layer in contact with the undoped polysilicon layer, and an insulating layer in contact with the undoped polysilicon layer. The undoped polysilicon layer is sandwiched between the doped polysilicon layer and the insulating layer.

Abstract: Structures and methods for flash memory transistors are formed with self-aligned drain/source contacts. The flash transistors are formed with a plurality of gate layers. An etch resistant layer(s) are deposited on top of the gate layers in the memory array transistors and on the gate layers of peripheral transistors. An additional oxide layer/spacer may be formed on the etch resistant layer to control the resulting transistor junction configuration. As a result within the same process various transistors may be formed satisfying various requirements. Contact holes to the drain and source regions of the memory and peripheral transistors are then formed. The etch resistant layer prevents the contact etchants from completely etching away the protective etch resistant layer surrounding the gate layers. The spacing between the drain/source contacts and the gate layers can be greatly reduced increasing the density of the memory array transistors and reducing chip size.

Abstract: A gate electrode is formed over but is insulated from a semiconductor body region for each of first and second transistors. Off-set spacers are formed along side-walls of the gate electrode of each of the first and second transistors. After forming the off-set spacers, a DDD implant is performed to form DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, main spacers are formed adjacent the off-set spacers of at least the first transistor. A LDD implant is performed to form LDD source and LDD drain regions for the second transistor. After forming the main spacers, a source/drain (S/D) implant is carried out to form a highly doped region within each of the DDD drain and DDD source regions and each of the LDD drain and LDD source regions.

Abstract: A non-volatile memory cell includes a first insulating layer over a substrate region, and a floating gate. The floating gate includes a first polysilicon layer over the first insulating layer and a second polysilicon layer over and in contact with the first polysilicon layer. The first polysilicon layer has a predetermined doping concentration and the second polysilicon layer has a doping concentration which decreases in a direction away from an interface between the first and second polysilicon layers. A second insulating layer overlies and is in contact with the second polysilicon layer. A control gate includes a third polysilicon layer over and in contact with the second insulating layer, and a fourth polysilicon layer over and in contact with the third polysilicon layer. The fourth polysilicon layer has a predetermined doping concentration, and the third polysilicon layer has a doping concentration which decreases in a direction away from an interface between the third and fourth polysilicon layers.

Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

Abstract: The present invention provides non-volatile memory cell transistors that have increased control-to-floating gate coupling coefficients due to a non-uniform gate surface area. In memory cells of the present invention, the floating gate is formed with a non-flat, non-uniform surface, which significantly increases the surface area interface between the floating gate and the inter-gate dielectric as well as the surface area interface between the inter-gate dielectric and the control gate. As a result, the inter-gate capacitance and the gate coupling coefficient are significantly increased. A high gate coupling coefficient allows the creation of small sized high performance memory cells that have high program and erase efficiency and read speed and can function at lower operation voltages. Higher gate coupling ratio allows also lowering operation voltages of memory cell which simplifies flash chip design, especially for lower power supply voltages.

Abstract: In one embodiment of the present invention, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.

Abstract: A frame of an electric cart includes a front part, and a rear part. A head tube, a seat support a securing combination, and front wheels are disposed at the front part. Rear wheels are disposed the rear ends of the rear part. Shock absorbers are connected to the rear part at lower ends. The rear part is connected to the front part with the front ends being pivoted to pivotal members formed at intermediate portions of the lateral sides of the base, and with upper ends of the shock absorbers being connected to the securing combination. The pivotal members are arranged nearer the front of the front part than the seat support so that distance from the rear wheels to the pivotal members is increased, thus helping reduce a range within which the rear part will vibrate when the cart moves along an uneven surface.

Abstract: A frame of an electric cart includes a front part, and a rear part. A head tube, a seat support, a securing combination, and front wheels are disposed at the front part. Rear wheels are disposed the rear ends of the rear part. Shock absorbers are connected to the rear part at lower ends. The rear part is connected to the front part with the front ends being pivoted to pivotal members formed at intermediate portions of the lateral sides of the base, and with upper ends of the shock absorbers being connected to the securing combination. The pivotal members are arranged nearer the front of the front part than the seat support so that distance from the rear wheels to the pivotal members is increased, thus helping reduce a range within which the rear part will vibrate when the cart moves along an uneven surface.

Abstract: A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.

Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

Abstract: A frame of an electric cart for the handicapped includes a front part and a rear part. The front part has several parallel connecting tubes, and the rear part also has parallel connecting tubes each corresponding to one of the tubes of the front part. The front tubes are inserted into the rear tubes, and bolts are screwed into screw holes formed alongside the tubes such that the front part and the rear parts are joined together. The length of the frame can be changed by means of adjusting the position of the front part in relation to the rear part.

Abstract: In accordance with an embodiment of the present invention, a semiconductor structure includes an undoped polysilicon layer, a doped polysilicon layer in contact with the undoped polysilicon layer, and an insulating layer in contact with the undoped polysilicon layer. The undoped polysilicon layer is sandwiched between the doped polysilicon layer and the insulating layer.

Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

Abstract: A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method comprises lowering the control gate to a potential of about −9 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential of about 9 volts.

Abstract: Structures and methods for flash memory transistors are formed with self-aligned drain/source contacts. The flash transistors are formed with a plurality of gate layers. An etch resistant layer(s) are deposited on top of the gate layers in the memory array transistors and on the gate layers of peripheral transistors. An additional oxide layer/spacer may be formed on the etch resistant layer to control the resulting transistor junction configuration. As a result within the same process various transistors may be formed satisfying various requirements. Contact holes to the drain and source regions of the memory and peripheral transistors are then formed. The etch resistant layer prevents the contact etchants from completely etching away the protective etch resistant layer surrounding the gate layers. The spacing between the drain/source contacts and the gate layers can be greatly reduced increasing the density of the memory array transistors and reducing chip size.

Abstract: An abrupt drain junction and a graded source junction are fabricated using a common diffusion step, wherein the common diffusion step is used to create both the drain junction-and the source junction. The common diffusion step is accomplished while an oxide spacer is present over a gate stack, prior to the common diffusion step, resulting in faster source diffusion and a graded source junction, while the slower diffusion in the drain region results in an abrupt drain junction. The oxide spacer moves the drain junction further away from the gate stack to allow for greater cell densities.