Patents by Inventor Artur ANTONYAN
Artur ANTONYAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10622066Abstract: A resistive memory device according to an example embodiment of the inventive concepts includes: a cell array including a first section and a second section; a first column switch circuit connected to a memory cell and a reference cell of the first section through first bit lines; a second column switch circuit connected to a memory cell and a reference cell of the second section through second bit lines; and a column decoder configured to control the first and second column switch circuits such that one of the first bit lines connected to the memory cell and one of the second bit lines connected to the reference cell are selected according to a first column address, and one of the first bit lines connected to the reference cell and one of the second bit lines connected to the memory cell are selected according to a second column address.Type: GrantFiled: September 14, 2018Date of Patent: April 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Artur Antonyan
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Publication number: 20200090724Abstract: A memory device including a normal memory cell array including a first magneto-resistance memory cell that is connected to a first bit line, a first source line, and a first word line, and configured to receive a selection voltage through the first word line, a monitor memory cell array including a second magneto-resistance memory cell that is connected to a first signal line and a second signal line, a gate of a cell transistor of which is configured to receive a non-selection voltage, and a body bias generator configured to sense a leakage current flowing through the first signal line and control a body voltage provided to each of a body of a cell transistor of the first magneto-resistance memory cell and a body of the cell transistor of the second magneto-resistance memory cell based on the leakage current may be provided.Type: ApplicationFiled: April 22, 2019Publication date: March 19, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Artur Antonyan, Hyuntaek JUNG, Suk-Soo PYO
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Publication number: 20200082866Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.Type: ApplicationFiled: November 19, 2019Publication date: March 12, 2020Inventor: Artur Antonyan
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Patent number: 10535392Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.Type: GrantFiled: June 21, 2018Date of Patent: January 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Artur Antonyan
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Patent number: 10510393Abstract: Provided is a resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device including a cell array including the memory cell and a reference cell; a reference resistance circuit configured to be electrically connected to the reference cell; an offset current source circuit configured to add or draw an offset current to or from a read current provided to the reference resistance circuit; and a control circuit configured to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.Type: GrantFiled: August 31, 2018Date of Patent: December 17, 2019Assignee: Samsung Electronics Co., LtdInventors: Artur Antonyan, Suk-soo Pyo
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Publication number: 20190348096Abstract: A resistive memory device configured to calibrate a reference resistor includes a calibration resistor circuit including a calibration resistor, a first reference resistor, a first sense amplifier configured to compare input currents, a first switch set including a plurality of switches, and a controller configured to control the first switch set to allow the first sense amplifier to compare a first reference current passing through the first reference resistor with a first read current passing through a first memory cell during a read operation and compare the first reference current with a first calibration current passing through the calibration resistor during a calibrate operation. A path of the first reference current during the read operation is different from a path of the first reference current during the calibrate operation.Type: ApplicationFiled: May 1, 2019Publication date: November 14, 2019Inventors: ARTUR ANTONYAN, HYUN-TAEK JUNG
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Publication number: 20190348118Abstract: A resistive memory device includes a plurality of word lines, a plurality of reference cells, a plurality of first resistive memory cells, a plurality of second resistive memory cells maintained in an off state, a read circuit configured to provide a first read current to the first resistive memory cells and provide a second read current to the reference cells while one of the first resistive memory cells is selected to perform a read operation, and a compensation circuit configured to provide a compensation current based on a first leakage current from the off resistive memory cells to the reference cells to compensate for a second leakage current generated by the unselected first resistive memory cells. Each reference cell is connected to one of the word lines and each of the first resistive memory cells are connected to one of the word lines.Type: ApplicationFiled: September 13, 2018Publication date: November 14, 2019Inventor: ARTUR ANTONYAN
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Patent number: 10453532Abstract: A resistive memory device includes a plurality of word lines, a plurality of reference cells, a plurality of first resistive memory cells, a plurality of second resistive memory cells maintained in an off state, a read circuit configured to provide a first read current to the first resistive memory cells and provide a second read current to the reference cells while one of the first resistive memory cells is selected to perform a read operation, and a compensation circuit configured to provide a compensation current based on a first leakage current from the off resistive memory cells to the reference cells to compensate for a second leakage current generated by the unselected first resistive memory cells. Each reference cell is connected to one of the word lines and each of the first resistive memory cells are connected to one of the word lines.Type: GrantFiled: September 13, 2018Date of Patent: October 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Artur Antonyan
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Publication number: 20190287603Abstract: Provided is a control signal generator for a sense amplifier, the control signal generator including a replica circuit including replica transistors corresponding to transistors included in the sense amplifier, and configured to receive at least one input signal of the sense amplifier and a first control signal for enabling a sensing operation by the sense amplifier; and an amplifying circuit configured to output, by amplifying an output signal from the replica circuit, a second control signal for enabling an amplifying operation by the sense amplifier after the sensing operation is enabled.Type: ApplicationFiled: February 22, 2019Publication date: September 19, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Artur Antonyan, Hyun-taek Jung
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Publication number: 20190287574Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected to the memory cell array through word lines, a column decoder that is connected to the memory cell array through bit lines and source lines, a write driver that transfers a write voltage to a bit line, which is selected by the column decoder, from among the bit lines by using a gate voltage in a write operation, and control logic that generates the gate voltage. The gate voltage is higher than the write voltage.Type: ApplicationFiled: June 6, 2019Publication date: September 19, 2019Inventor: Artur ANTONYAN
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Patent number: 10360948Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected to the memory cell array through word lines, a column decoder that is connected to the memory cell array through bit lines and source lines, a write driver that transfers a write voltage to a bit line, which is selected by the column decoder, from among the bit lines by using a gate voltage in a write operation, and control logic that generates the gate voltage. The gate voltage is higher than the write voltage.Type: GrantFiled: May 25, 2018Date of Patent: July 23, 2019Assignee: Samsung Electronics Co., Ltd.Inventor: Artur Antonyan
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Publication number: 20190088299Abstract: Provided is a resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device including a cell array including the memory cell and a reference cell; a reference resistance circuit configured to be electrically connected to the reference cell; an offset current source circuit configured to add or draw an offset current to or from a read current provided to the reference resistance circuit; and a control circuit configured to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.Type: ApplicationFiled: August 31, 2018Publication date: March 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Artur ANTONYAN, Suk-soo PYO
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Publication number: 20190088328Abstract: A resistive memory device according to an example embodiment of the inventive concepts includes: a cell array including a first section and a second section; a first column switch circuit connected to a memory cell and a reference cell of the first section through first bit lines; a second column switch circuit connected to a memory cell and a reference cell of the second section through second bit lines; and a column decoder configured to control the first and second column switch circuits such that one of the first bit lines connected to the memory cell and one of the second bit lines connected to the reference cell are selected according to a first column address, and one of the first bit lines connected to the reference cell and one of the second bit lines connected to the memory cell are selected according to a second column address.Type: ApplicationFiled: September 14, 2018Publication date: March 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventor: Artur ANTONYAN
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Publication number: 20180374515Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected to the memory cell array through word lines, a column decoder that is connected to the memory cell array through bit lines and source lines, a write driver that transfers a write voltage to a bit line, which is selected by the column decoder, from among the bit lines by using a gate voltage in a write operation, and control logic that generates the gate voltage. The gate voltage is higher than the write voltage.Type: ApplicationFiled: May 25, 2018Publication date: December 27, 2018Inventor: Artur Antonyan
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Publication number: 20180374525Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.Type: ApplicationFiled: June 21, 2018Publication date: December 27, 2018Inventor: Artur ANTONYAN
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Patent number: 10008249Abstract: A semiconductor memory device includes a memory cell array comprising a plurality of spin torque transfer-magnetic random access memory (STT-MRAM) cells connected to a plurality of word lines, a plurality of bit lines and a plurality of sense lines. A peripheral circuitry supplies cell current to the memory cells during read/write operations, such that the cell current supplied to memory cells of a selected word line vary according to a position of a word line group including the selected word line.Type: GrantFiled: January 13, 2017Date of Patent: June 26, 2018Assignee: Samsung Electronics Co., Ltd.Inventor: Artur Antonyan
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Patent number: 9892773Abstract: A memory device includes a memory array including a plurality of sections, each including a plurality of memory cells and at least one reference cell. The memory device may also include a plurality of sense amplifier circuits respectively corresponding to the plurality of sections, and a plurality of switch circuits, each switch circuit connected between a respective section and sense amplifier circuit. Each switch circuit may be configured to select between communicatively connecting a first column of memory cells or a reference cell to a corresponding sense amplifier.Type: GrantFiled: June 19, 2015Date of Patent: February 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Artur Antonyan
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Publication number: 20170278556Abstract: A semiconductor memory device includes a memory cell array comprising a plurality of spin torque transfer-magnetic random access memory (STT-MRAM) cells connected to a plurality of word lines, a plurality of bit lines and a plurality of sense lines. A peripheral circuitry supplies cell current to the memory cells during read/write operations, such that the cell current supplied to memory cells of a selected word line vary according to a position of a word line group including the selected word line.Type: ApplicationFiled: January 13, 2017Publication date: September 28, 2017Inventor: ARTUR ANTONYAN
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Patent number: 9711203Abstract: A boosted voltage generator may include a difference voltage generator, a first charging circuit, a second charging circuit and a switch circuit. The difference voltage generator generates a difference voltage to a first node, based on a reference voltage and a power supply voltage. The first charging circuit, connected between the first node and a ground voltage, charges the difference voltage therein during a first phase in response to a first pulse signal. The second charging circuit, connected between the first node and the ground voltage, charges the difference voltage therein during a second phase in response to a second pulse signal. The switch circuit, connected to a second node in the first charging circuit, a third node in the second charging circuit and an output node, provides a boosted voltage following a target level to the output node during each of the first phase and the second phase.Type: GrantFiled: June 8, 2016Date of Patent: July 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Artur Antonyan
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Patent number: 9672895Abstract: A sense amplifier is provided which includes a first load supplied with a selection cell current from a read bit line connected to a selected memory cell; a second load supplied with a reference current from a reference read bit line connected to a reference cell, a resistance value of the second load being different from a resistance value of the first load; and a sensing unit configured to correct a level of the reference current based on a resistance ratio of the first and second loads and to compare the selection cell current and the corrected reference current.Type: GrantFiled: April 19, 2016Date of Patent: June 6, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Artur Antonyan