Resistive memory device including reference cell and operating method thereof
Provided is a resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device including a cell array including the memory cell and a reference cell; a reference resistance circuit configured to be electrically connected to the reference cell; an offset current source circuit configured to add or draw an offset current to or from a read current provided to the reference resistance circuit; and a control circuit configured to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.
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This application claims the benefit of Korean Patent Application Nos. 10-2017-0118844, filed on Sep. 15, 2017 and 10-2018-0020007, filed on Feb. 20, 2018, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference.
BACKGROUNDThe inventive concepts relate to a resistive memory device, and more particularly to a resistive memory device including a reference cell and a method of operating a resistive memory device.
A resistive memory device may store data in a memory cell that includes a variable resistance element. To detect data stored in a memory cell of a resistive memory device, for example, a read current may be supplied to the memory cell, and a voltage due to the read current and a variable resistive element of the memory cell may be detected.
In memory cells in which specific values are stored, the resistances of variable resistive elements may be scattered, and the scattering may fluctuate due to process voltage temperatures (PVT) or the like. Such a variation of a resistance spread may interfere with accurate reading of values stored in memory cells.
SUMMARYThe inventive concepts provide a resistive memory device and a method of operating the memory device for accurately reading a value stored in a memory cell by compensating for variations in the resistance of the memory cell.
According to an aspect of the inventive concepts, there is provided a resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device including a cell array including the memory cell and a reference cell; a reference resistance circuit configured to be electrically connected to the reference cell; an offset current source circuit configured to add or draw an offset current to or from a read current provided to the reference resistance circuit; and a control circuit configured to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.
According to another aspect of the inventive concepts, there is provided a resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device including a cell array including the memory cell through which a first read current passes and a reference cell through which a reference current passes; a current source circuit configured to generate the first read current and the second read current; an offset current source circuit configured to generate the reference current by adding or drawing an offset current to or from the second read current; and a control circuit configured to control the offset current source circuit to compensate for a variation of the resistance of the memory cell.
According to another aspect of the inventive concepts, there is provided a resistive memory device configured to outputs a value stored in a memory cell in response to a read command, the resistive memory device including a cell array including the memory cell through which a first read current passes and a reference cell through which a second read current passes; an offset current source circuit configured to generate a reference current by adding or drawing an offset current to or from the second read current; a reference resistance circuit that is electrically connected to the reference cell and through which the reference current passes; and a control circuit configured to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.
Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Below, example embodiments of the inventive concepts will be described clearly and in detail with reference to accompanying drawings to such an extent that an ordinary one in the art implements example embodiments of the inventive concepts.
Referring to
The cell array 110 may include a plurality of memory cells M. A memory cell M may include a variable resistive element (e.g., MTJ in
The cell array 110 may include a reference cell R used to determine a value stored in the memory cell M. For example, as shown in
The current source circuit 120 may provide a first read current I_RD1 and a second read current I_RD2 to the cell array 110. For example, in response to a read command, the current source circuit 120 may provide the first read current I_RD1 to the memory cell M and provide at least a part of the second read current I_RD2 to the reference cell R. In some example embodiments, the current source circuit 120 may generate the first read current I_RD1 and the second read current I_RD2 of a same magnitude. Furthermore, in some example embodiments, the current source circuit 120 may adjust the magnitude(s) of the first read current I_RD1 and/or the second read current I_RD2 under the control of the control circuit 160.
In response to a read command, the reference resistance circuit 130 may be electrically connected to the reference cell R and provide a resistance through which a reference current I_REF passes. As described below, the reference current I_REF may be a current generated as an offset current I_OFF is added to or drawn from the second read current I_RD2 generated by the current source circuit 120. For example, as shown in
The offset current circuit 140 may generate the reference current I_REF by adding or drawing the offset current I_OFF to or from the second read current I_RD2. The offset current circuit 140 may include at least one current source that generates the offset current I_OFF, and the magnitude of the offset current I_OFF may be adjusted according to a control signal CTRL provided from the control circuit 160. As described below, the offset current I_OFF may have a magnitude and a direction corresponding to the variation of a variable resistance element included in the memory cell M. In some example embodiments, the second read current I_RD2 may pass through the reference cell R as described below with reference to
The amplification circuit 150 may receive a read voltage V_RD and a reference voltage V_REF and may determine a value stored in the memory cell M based on the read voltage V_RD and the reference voltage V_REF. For example, the amplification circuit 150 may output a signal corresponding to the value stored in the memory cell M by comparing the read voltage V_RD with the reference voltage V_REF. The read voltage V_RD may include a voltage drop caused as the first read current I_RD1 provided by the current source circuit 120 passes through the memory cell M. Furthermore, the read voltage V_RD may include not only a voltage drop due to the memory cell M, but also a voltage drop caused by a parasitic resistance in a path through which the first read current I_RD1 passes (e.g., a column decoder 170a, a source line SLj, and a bit line BLj).
Similar to the read voltage V_RD, the reference voltage V_REF may include not only a voltage drop caused by the reference cell R, but also a voltage drop caused by a parasitic resistance in a path through which the second read current I_RD2 provided by the current source circuit 120 or the reference current I_REF passes (e.g., the column decoder 170a, a short-circuit source line SSL, and a short-circuit bit line SBL in
The control circuit 160 may control the offset current circuit 140 through the control signal CTRL. In some example embodiments, the control circuit 160 may generate the control signal CTRL to compensate for variations of the resistance of a variable resistance element included in the memory cell M based on PVT variations or the like. For example, when the variable resistance element included in the memory cell M has a resistance proportional to the temperature, that is, a positive temperature coefficient, the control circuit 160 may reduce the magnitude of the offset current I_OFF drawn from the second read current I_RD2 through the control signal CTRL, such that the reference current I_REF supplied to the reference resistance circuit 130 increases, or increase the magnitude of the offset current I_OFF added to the second read current I_RD2. On the other hand, when the variable resistance element included in the memory cell M has a resistance inversely proportional to the temperature, that is, a negative temperature coefficient, the control circuit 160 may increase the magnitude of the offset current I_OFF drawn from the second read current I_RD2 or reduce the magnitude of the offset current I_OFF added to the second read current I_RD2 through the control signal CTRL, such that the reference current I_REF supplied to the reference resistance circuit 130 decreases.
In some example embodiments, the control circuit 160 may receive information about the offset current I_OFF from the controller 200. For example, the controller 200 may estimate the magnitude of the offset current I_OFF used in an operation for reading the memory device 100 to compensate for process variations of the memory device 100 and provide information about the estimated offset current I_OFF to the memory device 100. The information about the estimated offset current I_OFF may be stored in a non-volatile memory device (e.g., NVM in
When the reference resistance RREF of the reference resistance circuit 130 is adjusted to compensate for variation of the resistance of the variable resistance element included in the memory cell M due to the PVT variations or the like, the resistance may be quantized due to adjustable limited resistances, and thus the accuracy of the compensation may be deteriorated. In addition, to provide a plurality of adjustable reference resistances, the reference resistance circuit 130 may include a plurality of resistors and switch devices, and thus space consumption and power consumption by the reference resistance circuit 130 may increase. On the other hand, in the case of compensating for a variation of the resistance of the variable resistance element included in the memory cell M through the offset current I_OFF of the offset current circuit 140, a highly accurate compensation may be expected due to the continuous characteristics of the offset current I_OFF based on a simple structure as described below.
As shown in
The variable resistance element MTJ may include a free layer FL and a pinned layer PL and may include a barrier layer BL between the free layer FL and the pinned layer PL. As indicated by the arrows in
The variable resistance element MTJ may have a relatively low resistance RP in the parallel state P and a relatively high resistance RAP in the anti-parallel state AP. In this specification, it is assumed that the memory cell M′ stores ‘0’ when the variable resistance element MTJ in the parallel state P has a low resistance RP and stores ‘1’ when the variable resistance element MTJ in the anti-parallel state AP has a high resistance RAP. Furthermore, in this specification, the resistance RP corresponding to ‘0’ may be referred to as a parallel resistance RP, whereas the resistance RAP corresponding to ‘1’ may be referred to as an anti-parallel resistance RAP.
The cell transistor CT may include a gate connected to a word line WLi and a source and a drain connected to the source line SLj and the variable resistance element MTJ. The cell transistor CT may electrically connect or disconnect the variable resistance element MTJ and the source line SLj according to a signal applied to the word line WLi. For example, to write ‘0’ to the memory cell M′ in a write operation, the cell transistor CT may be turned ON, and a current from the bit line BLj to the source line SLj may pass through the variable resistance element MTJ and the cell transistor CT. Furthermore, to write ‘1’ to the memory cell M′, the cell transistor CT may be turned ON, and a current from the source line SLj to the bit line BLj may pass through the cell transistor CT and the variable resistance element MTJ. In a read operation, the cell transistor CT may be turned ON and the current from the bit line BLj to the source line SLj or the current from the source line SLj to the bit line BLj, that is, the first read current I_RD1, may pass through the cell transistor CT and the variable resistance element MTJ. It is assumed herein that the first read current I_RD1 flows from the source line SLj to the bit line BLj.
Referring to
In the example of
The scattering of the reference resistances RREF may be shifted to the left at a high temperature to accurately read ‘1’ stored in the memory cell M′ even at a high temperature. As described above with reference to
Hereinafter, referring to
I_REF=I_RD2+I_OFF [Equation 1]
Accordingly, the positive offset current I_OFF may indicate that the reference current I_REF is generated as a current corresponding to the magnitude of the offset current I_OFF is added to the second read current I_RD2 (that is, I_REF>I_RD2). Meanwhile, the negative offset current I_OFF may indicate that the reference current I_REF is generated as a current corresponding to the magnitude of the offset current I_OFF is drawn from the second read current I_RD2 (that is, I_REF<I_RD2). Furthermore, the magnitude of the offset current I_OFF may be zero according to the control signal CTRL.
The cell array 110a may include the memory cell M and the reference cell R connected in common to the word line WLi. The memory cell M may be connected to the bit line BLj and the source line SLj, and the reference cell R may be connected to a shorting bit line SBL and a shorting source line SSL. The bit line BLj, the source line SLj, the shorting bit line SBL, and the shorting source line SSL may extend to the column decoder 170a. The memory cell M may include the variable resistance element MTJ and the cell transistor CT connected in series between the bit line BLj and the source line SLj, whereas the reference cell R may include the cell transistor CT connected to the shorting bit line SBL and the shorting source line SSL. Therefore, the shorting bit line SBL and the shorting source line SSL may be electrically short-circuited or opened by the cell transistor CT of the reference cell R, and such the reference cell R without a resistor may be referred to as a shorted cell.
To compensate for a voltage drop due to the bit line BLj and the source line SLj connected to the memory cell M, the reference cell R connected to the shorting bit line SBL and the shorting source line SSL may be disposed in the cell array 110a. As shown in
The column decoder 170a may route the bit line BLj, the source line SLj, the shorting bit line SBL, and the shorting source line SSL according to a column address COL. The column address COL may be generated from an address ADDR received from the controller 200 of
The amplification circuit 150a may be connected to nodes to which the first read current I_RD1 and the second read current I_RD2 are output from the current source circuit 120a and generate an output signal Q according to voltages of the nodes, that is, the read voltage V_RD and the reference voltage V_REF. The reference voltage V_REF may be determined based on the resistance value of the variable resistance element MTJ of the memory cell M and the first read current I_RD1, whereas the reference voltage V_REF may be determined based on the reference resistance value RREF and the reference current I_REF. The amplification circuit 150a may generate the output signal Q corresponding to ‘1’ when the read voltage V_RD is higher than the reference voltage V_REF and may generate the output signal Q corresponding to ‘0’ when the read voltage V_RD is lower than the reference voltage V_REF.
The offset current circuit 140a may include a first current source 141a providing a source current I_SC and a second current source 142a providing a sink current I_SK. Therefore, the offset current I_OFF may be equal to a difference between the source current I_SC and the sink current I_SK, as shown in Equation 2 below.
I_OFF=I_SC−I_SK [Equation 2]
The first current source 141a and/or the second current source 142a may adjust the source current I_SC and/or the sink current I_SK according to the control signal CTRL, thereby adjusting the offset current I_OFF. In some example embodiments, the offset current circuit 140a may include only one of the first current source 141a and the second current source 142a, as described below with reference to
As the offset current circuit 140b is disposed between the current source circuit 120b and the reference cell R, the reference current I_REF generated as the offset current I_OFF is reflected to the second read current I_RD2 may flow through the shorting source line SSL, the reference cell R, the shorting bit line SBL, and the reference resistance circuit 130b to the negative supply voltage VSS. The offset current circuit 140b may include a first current source 141b providing the source current I_SC and a second current source 142b providing the sink current I_SK, and the offset current I_OFF may be determined as shown in Equation 2. The first current source 141b and/or the second current source 142b may adjust the source current I_SC and/or the sink current I_SK according to the control signal CTRL, thereby adjusting the offset current I_OFF. In some example embodiments, unlike as shown in
As the offset current circuit 140c is disposed between the current source circuit 120c and the reference resistance circuit 130c, the reference current I_REF generated as the offset current I_OFF is reflected to the second read current I_RD2 may flow through the reference resistance circuit 130c, the shorting source line SSL, the reference cell R, and the shorting bit line SBL to the negative supply voltage VSS. The offset current circuit 140c may include a first current source 141c providing the source current I_SC and a second current source 142c providing the sink current I_SK, and the offset current I_OFF may be determined as shown in Equation 2. The first current source 141c and/or the second current source 142c may adjust the source current I_SC and/or the sink current I_SK according to the control signal CTRL, thereby adjusting the offset current I_OFF. In some example embodiments, unlike as shown in
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
In operation S200, an operation of generating a first read current I_RD1 and a second read current I_RD2 may be performed. For example, the current source circuit 120 of the memory device 100 may generate the first read current I_RD1 and the second read current I_RD2 in response to a read command. The first read current I_RD1 may be provided to the memory cell M of the cell array 110 and at least a part of the second read current I_RD2 may be provided to the reference cell R of the cell array 110. In some example embodiments, the first read current I_RD1 and the second read current I_RD2 may have a substantially same magnitude.
In operation S400, an operation for generating the offset current I_OFF according to a variation of the resistance of the memory cell M may be performed. For example, the control signal CTRL may be generated to compensate for the variation of the resistance of the memory cell M based on a process in which the memory device 100 is manufactured, an operating environment (e.g., supply voltage and temperature) of the memory device 100, etc., and the offset current circuit 140 may generate the offset current I_OFF according to the control signal CTRL. The reference current I_REF may be generated by increasing or decreasing the second read current I_RD2 due to the offset current I_OFF.
In operation S600, an operation for generating the read voltage V_RD and the reference voltage V_REF may be performed. For example, as the first read current I_RD1 passes through the memory cell M, the read voltage V_RD may be generated. Furthermore, in some example embodiments, the reference voltage V_REF may be generated as the second read current I_RD2 passes through the reference cell R and the reference current passes through the reference resistance circuit 130. In some example embodiments, the reference voltage V_REF may be generated as the reference current I_REF passes through the reference cell R and the reference resistance circuit 130.
In operation S800, an operation for determining a value stored in the memory cell M may be performed. For example, the amplification circuit 150 may receive the read voltage V_RD and the reference voltage V_REF, compare the read voltage V_RD with the reference voltage V_REF, and generate an output corresponding to the value stored in the memory cell M. As the variation of the resistance of the memory cell M is reflected to the reference voltage V_REF by the offset current I_OFF, the value stored in the memory cell M may be accurately read.
The core 310 may process instructions and may control operations of components included in the SoC 300. For example, the core 310 may drive an operating system and execute applications on the operating system by processing a series of instructions. The DSP 320 may generate useful data by processing a digital signal, e.g., a digital signal provided by the communication interface 350. The GPU 330 may generate data for an image to be output via a display device from image data provided by the internal memory 340 or encode image data.
The internal memory 340 may store data for operating the core 310, the DSP 320, and the GPU 330. The internal memory 340 may include a resistive memory device according to an example embodiment, and thus the internal memory 340 may exhibit high operational reliability by compensating for variations of the variable resistive element.
The communication interface 350 may provide a communication network or an interface for one-on-one communication. The memory interface 360 may provide an interface for an external memory of the SoC 300, e.g., a dynamic random access memory (DRAM), a flash memory, etc.
An interface 600 via which the memory system 400 and the host 500 communicate with each other may use electrical signals and/or optical signals and may include, but are not limited to, a serial advanced technology attachment (SATA) interface, a SATA express (SATAe) interface, a serial attached small computer system interface (serial attached SCSI; SAS), a peripheral component interconnect express (PCIe) interface, a non-volatile memory express (NVMe) interface, an advanced host controller interface (AHCI), or a combination thereof.
In some example embodiments, the memory system 400 may communicate with the host 500 by being removably coupled to the host 500. As a resistive memory, the memory device 420 may be a non-volatile memory, and the memory system 400 may be referred to as a storage system. For example, the memory system 400 may include, but is not limited to, a solid-state drive or solid-state disk (SSD), an embedded SSD (eSSD), a multimedia card (MMC), an embedded multimedia card (eMMC), or the like.
The controller 410 may control the memory device 420 in response to a request received from the host 500 via the interface 600. For example, in response to a write request, the controller 410 may write data received in association with the write request to the memory device 420 and, in response to a read request, provide data stored in the memory device 420 to the host 500.
The memory system 400 may include at least one memory device 420 and the memory device 420 may include a reference cell and memory cells having variable resistive elements. As described above with reference example embodiments, a variation of the resistance of a memory cell due to a manufacturing process of the memory device 420 and an operating environment of the memory device 420 or the memory system 400 may be simply and accurately compensated for by adjusting a reference current flowing through a reference resistor connected to a reference cell. Therefore, the memory device 420 may accurately provide a value stored in a memory cell to the controller 410 in response to a read command of the controller 410, thereby improving the operational reliability of the memory system 400.
While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
Claims
1. A resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device comprising:
- a cell array including the memory cell and a reference cell;
- a reference resistance circuit electrically connected to the reference cell;
- an offset current source circuit configured to generate an offset current based on a control signal, the offset current being combined with a read current provided to the reference resistance circuit to increase or decrease a magnitude of the read current; and
- a control circuit configured to generate the control signal to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.
2. The resistive memory device of claim 1,
- the control circuit is configured to generate the control signal to adjust a magnitude of the offset current based on a temperature of the resistive memory device.
3. The resistive memory device of claim 2, wherein
- the offset current source circuit is configured to adjust the magnitude of the offset current according to the control signal;
- the control circuit is configured to, generate a first signal proportional to temperature, generate a second signal inversely proportional to temperature, and generate the control signal as a weighted sum of the first signal and the second signal; and
- a weight of the weighted sum is determined according to temperature variation characteristics of the resistance of the memory cell.
4. The resistive memory device of claim 2, wherein
- the offset current source circuit is configured to adjust the magnitude of the offset current according to the control signal;
- the control circuit includes a look-up table; and
- the control circuit is further configured to generate the control signal from a temperature signal according to the temperature of the resistive memory device by referring to the look-up table.
5. The resistive memory device of claim 1, further comprising:
- a non-volatile memory configured to store process information,
- wherein the control circuit is configured to generate the control signal to adjust a magnitude of the offset current based on the process information by accessing the non-volatile memory.
6. The resistive memory device of claim 1, wherein the control circuit is configured to generate the control signal to adjust a magnitude of the offset current based on a magnitude of a positive supply voltage of the resistive memory device.
7. A resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device comprising:
- a cell array including the memory cell through which a first read current passes and a reference cell through which a reference current passes;
- a current source circuit configured to generate the first read current and a second read current;
- an offset current source circuit configured to generate the reference current by outputting an offset current based on a control signal, the offset current being combined with the second read current, the reference current having a magnitude higher or lower than the second read current; and
- a control circuit configured to generate the control signal to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.
8. The resistive memory device of claim 7, further comprising:
- a reference resistance circuit electrically connected to the reference cell and through which the reference current passes.
9. The resistive memory device of claim 7, wherein
- the control circuit is configured to generate the control signal to adjust a magnitude of the offset current based on a temperature of the resistive memory device.
10. The resistive memory device of claim 9, wherein
- the offset current source circuit is configured to adjust the magnitude of the offset current according to the control signal;
- the control circuit is configured to, generate a first signal proportional to temperature, generate a second signal inversely proportional to temperature, and generate the control signal as a weighted sum of the first signal and the second signal; and
- a weight of the weighted sum is determined according to temperature variation characteristics of the resistance of the memory cell.
11. The resistive memory device of claim 9, wherein
- the offset current source circuit is configured to adjust the magnitude of the offset current according to the control signal; and
- the control circuit includes a look-up table; and
- the control circuit is further configured to generate the control signal from a temperature signal according to the temperature of the resistive memory device by referring to the look-up table.
12. The resistive memory device of claim 7, further comprising:
- a non-volatile memory configured to store process information,
- wherein the control circuit is configured to generate the control signal to adjust a magnitude of the offset current based on the process information by accessing the non-volatile memory.
13. The resistive memory device of claim 7, wherein the control circuit is configured to generate the control signal to adjust a magnitude of the offset current based on a magnitude of a positive supply voltage of the resistive memory device.
14. The resistive memory device of claim 7, wherein the first read current and the second read current are approximately the same.
15. A resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device comprising:
- a cell array including the memory cell through which a first read current passes and a reference cell through which a second read current passes;
- an offset current source circuit configured to generate a reference current by outputting an offset current based on a control signal, the offset current being combined with the second read current, the reference current having a magnitude higher or lower than the second read current;
- a reference resistance circuit electrically connected to the reference cell and through which the reference current passes; and
- a control circuit configured to generate the control signal to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.
16. The resistive memory device of claim 15, wherein
- the control circuit is configured to generate the control signal to adjust a magnitude of the offset current based on a temperature of the resistive memory device.
17. The resistive memory device of claim 16, wherein
- the offset current source circuit is configured to adjust the magnitude of the offset current according to the control signal;
- the control circuit is configured to, generate a first signal proportional to temperature, generate a second signal inversely proportional to temperature, and generate the control signal as a weighted sum of the first signal and the second signal; and
- a weight of the weighted sum is determined according to temperature variation characteristics of the resistance of the memory cell.
18. The resistive memory device of claim 16, wherein
- the offset current source circuit is configured to adjust the magnitude of the offset current according to the control signal;
- the control circuit includes a look-up table; and
- the control circuit is configured to generate the control signal from a temperature signal according to the temperature of the resistive memory device by referring to the look-up table.
19. The resistive memory device of claim 15, further comprising:
- a non-volatile memory configured to store process information,
- wherein the control circuit is configured to generate the control signal to adjust a magnitude of the offset current based on the process information by accessing the non-volatile memory.
20. The resistive memory device of claim 15, wherein the control circuit is configured to generate the control signal to adjust a magnitude of the offset current based on a magnitude of a positive supply voltage of the resistive memory device.
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Type: Grant
Filed: Aug 31, 2018
Date of Patent: Dec 17, 2019
Patent Publication Number: 20190088299
Assignee: Samsung Electronics Co., Ltd (Gyeonggi-do)
Inventors: Artur Antonyan (Suwon-si), Suk-soo Pyo (Hwaseong-si)
Primary Examiner: Thong Q Le
Application Number: 16/118,774
International Classification: G11C 11/00 (20060101); G11C 11/16 (20060101); G11C 13/00 (20060101); H01L 43/08 (20060101); G11C 7/04 (20060101); G11C 7/08 (20060101);