Abstract: Provided are systems, methods, and apparatuses for transferring computational tasks. In one or more examples, the systems, methods, and apparatuses include a first host configured to detect a trigger to offload instruction code from the first host to a second host; identify, based on the trigger, an address translation binding for the instruction code and an address translation binding for application data associated with the instruction code; copy the address translation binding for the instruction code and the address translation binding for the application data to a memory; and transfer control of execution of the instruction code to the second host based on the copying.

Abstract: A forklift autonomous operation system is disclosed. The forklift autonomous operation system includes a forklift having a load handling system, the load handling system including a mast and a plurality of forks and a camera, coupled to the load handling system, for obtaining visual input data of an environment. Further, the system includes a plurality of sensors coupled to the forklift for obtaining sensor data and a control system configured to process the visual input data and the sensor data.

Abstract: The present disclosure relates to mTOR inhibitors. Specifically, the embodiments are directed to compounds and compositions inhibiting mTOR, methods of treating diseases mediated by mTOR, and methods of synthesizing these compounds.

Abstract: A method, programming product, and/or system is disclosed for identifying flaws in integrated circuits, e.g., processors, that includes: selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate; tracing back the selected one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more selected physical design VHDL (PD-VHDL) code lines; logically navigating across the one or more selected PD-VHDL code lines to one or more corresponding normalized VHDL (NVDHL) code lines; and tracing back the one or more corresponding NHVDL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.

Abstract: A computer-implemented method for instrumentation-assisted debugging is provided. The computer-implemented method includes compiling a hardware design to generate a compiled design, generating, from the compiled design, code for the hardware design and debug assist elements, feeding the code into a vendor emulation flow that outputs a vendor waveform and transforming the vendor waveform into a logic simulation waveform that is compatible with a hardware design language (HDL) using the debug assist elements for hardware logic debugging.

Abstract: A method for generating a probability for a first action of a sporting event by implementing a feature set, the method including: obtaining an initial set of data relating to the first action of a sporting event, the initial set of data including at least a position of a first player on a surface and a position of a target area on the surface; generating, by a machine learning model, an initial projected scoring probability based on the initial set of data; generating a feature set relating to the sporting event; and modifying, by the machine learning model, the initial projected scoring probability to an updated scoring probability using the feature set.

Abstract: The present disclosure presents system and methods for obtaining multimodal input data of a subject, wherein the multimodal input data comprises at least two input modalities of data; extracting features from the multimodal input data; learning multimodal signal correlations and source latent distribution alignment from the extracted features of the multimodal input data; training and optimizing a multimodal machine learning algorithm on input labeled data to learn local features of each modality of the multimodal input data; and/or executing, by a computer system, the trained multimodal machine learning algorithm to predict a cognitive state or disorder of the subject using the learned multimodal signal correlations and source latent distribution alignment.

Abstract: According to one embodiment, a method, computer system, and computer program product for providing memories based on a process of machine learning is provided. The embodiment may include collecting biometric data from a subject in response to an event. The embodiment may also include building a graph based on the collected biometric data. The embodiment may further include training a machine learning model based on the built graph. The embodiment may also include providing a memory to a user based on the machine learning model.

Abstract: Automatic verification of a hardware cryptographic implementation includes receiving a reference implementation of a cryptographic algorithm, receiving test case data associated with the cryptographic algorithm, generating a stimulus based upon the test case data, applying the stimulus to the reference implementation using a simulation model to generate a first intermediate state result, applying the stimulus to a hardware implementation of the cryptographic algorithm using the simulation model to generate a second intermediate state result, and generating a verification result based upon a comparison of the first intermediate state result and the second intermediate state result.

Abstract: Systems and methods for configuring a robot to scan for features are disclosed herein. According to at least one non-limiting exemplary embodiment, a robot may be configured to scan for features within an environment by producing various computer-readable maps which may be annotated to facilitate organized and accurate feature scanning.

Abstract: An approach for modifying in real-time by removing or reinforcing stroboscopic effect from images associated with a viewing experience is disclosed. The approach includes identifying video clips, detecting environmental parameters and calculating display setting. The approach also analyzes display setting using recommendation from GAN, output displaying setting on an AR display and receiving feedback from user.

Abstract: A computer receives determines a mobile device requires a recharge, where the mobile device have a solar cell and an imaging device. The computer identifies an object with a low diffusion rate. The computer recharges the mobile device, based on determining that the mobile device receiving the solar energy from the identified object.

Abstract: To increase the efficiency of electronic design automation, a register transfer level debug application client entity requests, from a register transfer level source navigator server, combined register transfer level and hardware aspect metadata including debug instrumentation. The register transfer level debug application client entity receives, from the register transfer level source navigator server, the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity transforms the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity renders the transformed combined register transfer level and hardware aspect metadata including the debug instrumentation.

Abstract: A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.

Abstract: A method, programming product, and/or system is disclosed for identifying flaws in integrated circuits, e.g., processors, that includes: selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate; tracing back the selected one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more selected physical design VHDL (PD-VHDL) code lines; logically navigating across the one or more selected PD-VHDL code lines to one or more corresponding normalized VHDL (NVDHL) code lines; and tracing back the one or more corresponding NHVDL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.

Abstract: A method includes communicating a first stream of a video comprising first and second objects to a device. The first stream has a first resolution. The method also includes communicating a second stream to the device. The second stream indicates that the first object is contextual and that the second object is non-contextual. The method further includes, after a decrease in bandwidth, communicating a third stream of the video to the device. The third stream has a second resolution that is lower than the first resolution. When the video is presented for display using the third stream and based on the second stream indicating that the first object is contextual and that the second object is non-contextual, the first object is presented in the first resolution and the second object is presented in the second resolution.

Abstract: An approach for modifying in real-time by removing or reinforcing stroboscopic effect from images associated with a viewing experience is disclosed. The approach includes identifying video clips, detecting environmental parameters and calculating display setting. The approach also analyzes display setting using recommendation from GAN, output displaying setting on an AR display and receiving feedback from user.

Abstract: A method for collaborative logic designing and debugging of a circuit includes initiating, via a session manager, a hardware debug session that includes a plurality of instances of client applications that can access one or more source-codes associated with a logic design of the circuit, the plurality of instances of client applications configured to replicate an execution state of the logic design. The method also includes analyzing, using an instance of a first client application from the plurality of instances of client applications, a defect in the logic design based on the execution state of the logic design. The method also includes editing, using an instance of a second client application from the plurality of instances of client applications, the one or more source-codes, to repair the defect in the logic design.

Abstract: To increase the efficiency of electronic design automation, a register transfer level debug application client entity requests, from a register transfer level source navigator server, combined register transfer level and hardware aspect metadata including debug instrumentation. The register transfer level debug application client entity receives, from the register transfer level source navigator server, the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity transforms the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity renders the transformed combined register transfer level and hardware aspect metadata including the debug instrumentation.

Abstract: A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.