Patents by Inventor Arun Joseph
Arun Joseph has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170316119Abstract: A method for analyzing power in a circuit includes identifying equivalent elements in a source netlist representing the circuit. Abstract elements are formed combining the equivalent elements of the source netlist. A reduced netlist is formed, substituting the abstract elements in the reduced netlist for the collective equivalent elements in the source netlist. Metrics or properties associated with equivalent elements of the source netlist are combined and associated, in the reduced netlist, with the abstract elements. The reduced netlist can be analyzed with results equivalent to analyzing the source netlist.Type: ApplicationFiled: April 27, 2016Publication date: November 2, 2017Inventors: Arun Joseph, Rahul M. Rao
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Publication number: 20170315605Abstract: A method for analyzing power in a circuit includes identifying equivalent elements in a source netlist representing the circuit. Abstract elements are formed combining the equivalent elements of the source netlist. A reduced netlist is formed, substituting the abstract elements in the reduced netlist for the collective equivalent elements in the source netlist. Metrics or properties associated with equivalent elements of the source netlist are combined and associated, in the reduced netlist, with the abstract elements. The reduced netlist can be analyzed with results equivalent to analyzing the source netlist.Type: ApplicationFiled: December 20, 2016Publication date: November 2, 2017Inventors: Arun Joseph, Rahul M. Rao
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Patent number: 9754058Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.Type: GrantFiled: November 5, 2015Date of Patent: September 5, 2017Assignee: International Business Machines CorporationInventors: Arun Joseph, Arya Madhusoodanan, Rahul M. Rao, Suriya T. Skariah
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Publication number: 20170235856Abstract: A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.Type: ApplicationFiled: February 11, 2016Publication date: August 17, 2017Inventors: Anand Haridass, Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao
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Patent number: 9697306Abstract: A computer program product includes program instructions to: Receive a unit including register transfer level content for a component of an integrated circuit and one or more IP blocks; Select one or more input pins for each IP block; Assign a numerical value of either zero or one to each of the one or more input pins to yield at least one numerical sequence; For each numerical sequence, perform a check to yield a number of fails, wherein the check is formal verification of each of the one or more IP blocks; Determine a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails; Set the one or more input pins to the simulation condition for power modeling of the unit; and Determine a number of design errors of the unit based on the simulation condition.Type: GrantFiled: July 12, 2016Date of Patent: July 4, 2017Assignee: International Business Machines CorporationInventors: Anand Haridass, Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao
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Patent number: 9684465Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.Type: GrantFiled: March 28, 2014Date of Patent: June 20, 2017Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Anand Haridass, Arun Joseph
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Publication number: 20170132342Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.Type: ApplicationFiled: November 5, 2015Publication date: May 11, 2017Inventors: Arun Joseph, Arya Madhusoodanan, Rahul M. Rao, Suriya T. Skariah
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Publication number: 20170132343Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.Type: ApplicationFiled: August 23, 2016Publication date: May 11, 2017Inventors: Arun Joseph, Arya Madhusoodanan, Rahul M. Rao, Suriya T. Skariah
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Patent number: 9606741Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.Type: GrantFiled: May 16, 2014Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Anand Haridass, Arun Joseph
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Publication number: 20170023639Abstract: A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.Type: ApplicationFiled: July 22, 2015Publication date: January 26, 2017Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Anand Haridass, Arun Joseph, Charles R. Lefurgy, Spandana V. Rachamalla
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Publication number: 20170004234Abstract: Generating a contributor-based power abstract for a device, including: identifying a clock power component for each of a plurality of clock gating domains, identifying a switching characteristic for each of the clock gating domains, combining the switching characteristics for all of the clock gating domains into a domain combination list, performing a per-case simulation based at least on the domain combination list, calculating an effective capacitance for each of the clock gating domains based at least on the per-case simulation, and generating a power abstract for each of the clock gating domains based at least on the effective capacitance.Type: ApplicationFiled: July 1, 2015Publication date: January 5, 2017Inventors: NAGASHYAMALA R. DHANWADA, WILLIAM W. DUNGAN, DAVID J. HATHAWAY, ARUN JOSEPH, GAURAV MITTAL, RICARDO H. NIGAGLIONI
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Patent number: 9471239Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.Type: GrantFiled: April 26, 2016Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Anand Haridass, Arun Joseph
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Patent number: 9460251Abstract: A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.Type: GrantFiled: April 27, 2016Date of Patent: October 4, 2016Assignee: International Business Machines CorporationInventors: Anand Haridass, Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao
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Publication number: 20160224265Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.Type: ApplicationFiled: April 26, 2016Publication date: August 4, 2016Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Anand Haridass, Arun Joseph
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Patent number: 9288042Abstract: A method, computer program product, and computing system for generating, by a computing device, a key, wherein the key includes at least one of an encryption key and an authentication key. One or more credentials may be generated to access a Secure KeyStore storing the key, wherein the one or more credentials may include one or more stable system values, and wherein the one or more stable system values may include one or more virtual values and one or more hardware values. The one or more stable system values may be provided to the Secure KeyStore to retrieve the key.Type: GrantFiled: March 14, 2014Date of Patent: March 15, 2016Assignee: EMC CorporationInventors: Manish Madhukar, Jeffrey A. Brown, Arun Joseph, Rahul D. Pradhan, Jaleel A. Kazi, Jeffrey A. Blakeslee
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Patent number: 9217771Abstract: A system, method and computer program product for enabling efficient and accurate post-silicon leakage power characterization of semiconductor chips at very high temperatures. The system and method can be used to estimate dynamic power usage at a sub-component level. The system and method determines leakage power during test time while running a workload in a manner such that a wider range of temperatures can be characterized on a tester that does not have precise temperature control, i.e., does not require or use external heaters. Additional power management functionality for a semiconductor device is provided while running a workload that breaks down total power measured into workload dependent and workload-independent subcomponents.Type: GrantFiled: January 14, 2014Date of Patent: December 22, 2015Assignee: International Business Machines CorporationInventors: Nagashyamala R. Dhanwada, Anand Haridass, Arun Joseph, Charles R. Lefurgy, Diwesh Pandey
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Publication number: 20150277543Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.Type: ApplicationFiled: May 16, 2014Publication date: October 1, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Anand Haridass, Arun Joseph
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Publication number: 20150277542Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Anand Haridass, Arun Joseph
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Publication number: 20150198660Abstract: A system, method and computer program product for enabling efficient and accurate post-silicon leakage power characterization of semiconductor chips at very high temperatures. The system and method can be used to estimate dynamic power usage at a sub-component level. The system and method determines leakage power during test time while running a workload in a manner such that a wider range of temperatures can be characterized on a tester that does not have precise temperature control, i.e., does not require or use external heaters. Additional power management functionality for a semiconductor device is provided while running a workload that breaks down total power measured into workload dependent and workload-independent subcomponents.Type: ApplicationFiled: January 14, 2014Publication date: July 16, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nagashyamala R. Dhanwada, Anand Haridass, Arun Joseph, Charles R. Lefurgy, Diwesh Pandey
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Publication number: 20120110303Abstract: A system and method for process synchronization in a multi-core computer system. A separate non-caching memory enables a method to synchronize processes executing on multiple processor cores. Since only a very small amount (a few number of bytes), is needed for the synchronization, it is possible to extend the method for inter-processor core message passing by allocating dedicated address space of the on-chip memory for each processor with exclusive write access. Each of the multiple processor cores maintains a dedicated cache while maintaining coherency with the non-cache shared memory.Type: ApplicationFiled: October 28, 2010Publication date: May 3, 2012Applicant: International Business Machines CorporationInventors: Nagashyamala (Nagu) R. Dhanwada, Arun Joseph