Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.

Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.

Abstract: A system, method and computer program product for enabling efficient and accurate post-silicon leakage power characterization of semiconductor chips at very high temperatures. The system and method can be used to estimate dynamic power usage at a sub-component level. The system and method determines leakage power during test time while running a workload in a manner such that a wider range of temperatures can be characterized on a tester that does not have precise temperature control, i.e., does not require or use external heaters. Additional power management functionality for a semiconductor device is provided while running a workload that breaks down total power measured into workload dependent and workload-independent subcomponents.

Abstract: A system and method for process synchronization in a multi-core computer system. A separate non-caching memory enables a method to synchronize processes executing on multiple processor cores. Since only a very small amount (a few number of bytes), is needed for the synchronization, it is possible to extend the method for inter-processor core message passing by allocating dedicated address space of the on-chip memory for each processor with exclusive write access. Each of the multiple processor cores maintains a dedicated cache while maintaining coherency with the non-cache shared memory.