Abstract: A method of operating a Universal Serial Bus Power Delivery (USB-PD) power converter includes responsive to detecting an absence of a load device sending a low power mode signal from a secondary-side controller, coupled to control a secondary-side of the USB-PD power converter, to a primary-side controller coupled to control a primary-side of the USB-PD power converter, and transitioning the secondary-side controller from a secondary-side active mode to a secondary-side low power mode, transitioning the primary-side controller from a primary-side active mode to a primary-side low power mode responsive to receiving the low power mode signal, responsive to detecting a connection of the load device sending an active mode signal from the secondary-side controller to the primary-side controller, and transitioning the secondary-side controller from the secondary-side low power mode to the secondary-side active mode, and transitioning the primary-side controller from the primary-side low power mode to the primary-si

Abstract: Controlling power factor correction (PFC) in a secondary-controlled alternating current (AC) to direct current (DC) (AC-DC) power adapter is described. In one embodiment, an apparatus includes a transformer, a primary-side controller coupled to the transformer, a PFC component coupled to the primary-side controller, and a secondary-side controller coupled to the transformer. The secondary-side controller is configured at least to obtain data informative of an amount of power, and control, based on the amount of power, a PFC operating mode of the PFC component.

Abstract: A fly-back converter and method of operating is provided to eliminate cross-conduction between a power-switch (PS) on a primary side of a transformer and a synchronous-rectifier (SR) on a secondary side when operating in continuous conduction mode. Generally, the method includes turning on the SR when a drain voltage of the SR drops to a negative voltage followed by a rise in the SR-drain-voltage at a first slope as a current is drawn from the secondary side of the transformer through the SR. When the PS is turned on before the transformer is completely discharged cross-conduction causes a change in the rise of the drain voltage to a second slope greater than the first slope. By turning off the SR within 50 ns of the change in the rise of the drain voltage, cross-conduction is minimized or eliminated without receiving turn-on information from a controller operating the PS.

Abstract: A mode-transition architecture for USB controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes a controller coupled to a slope compensation circuit, the controller to detect a transition of a buck-boost converter from a first mode having a first duty cycle to a second mode having a second duty cycle that is less or more than the first duty cycle. The controller controls the slope compensation circuit to nullify an error in an output caused by the transition. The controller can cause the slope compensation circuit to apply a charge stored in a capacitor during a first cycle to start a second cycle with a higher voltage than the first cycle.

Abstract: An USB-PD power converter with primary and secondary side controllers that bidirectionally communicate with each other. In one embodiment, the USB-PD power converter has a first transformer in data communication with the primary-side controller and the secondary-side controller. The secondary-side controller is configured to generate control signals and receive acknowledgement signals from the primary-side controller via the first transformer. The primary-side controller is configured to generate the acknowledgment signals and receive the control signals from the secondary-side controller via the first transformer.

Abstract: Techniques are provided for discharge of a universal serial bus voltage. A determination is made that the universal serial bus voltage has exceeded a threshold. Accordingly, initiation of a discharge operation is triggered to discharge the universal serial bus voltage. The discharge operation includes applying incrementally increasing voltage reference values according to a periodic interval to an amplifier until a discharge trigger point is reached. The amplifier outputs a voltage signal to a gate driver that controls a gate of a transistor that provides a discharge path for the universal serial bus voltage to discharge. In response to reaching the discharge trigger point, the incremental increasing of the voltage reference values applied to the amplifier is stopped.

Abstract: A flyback-converter with synchronous-rectifier (SR) sense architecture is provided. A secondary side controller includes a SR-sense pin coupled through an external resistor to a drain of an SR on the secondary-side, a negative-sensing-detector, a peak-detector, a zero-crossing-detector, all coupled to the pin, and a resistor network (Rn) coupled between the pin and ground. The Rn includes a first resistor (R1) to couple the pin and to ground through a first switch (S1) during negative-sensing to divide a voltage (VSR_drain) coupled to the pin, and a second, higher resistance resistor (R2) to couple the pin to ground through a second switch (S2) during peak-detection to divide VSR_draincoupled to the pin. S1 and S2 are controlled by register-transfer-level circuit in the SSC. A line-feed-forward (LFF) circuit is coupled to the pin through an active diode to receive an undivided VSR_drain and mirrors diode current to control the converter in LFF mode.

Abstract: Secondary side peak current control mode flyback converters are described. In one embodiment, an apparatus includes a flyback converter including a flyback transformer and a signal transformer, a primary side including a primary-side controller coupled to a power switch, the flyback transformer and the signal transformer, and a secondary side including a secondary-side controller coupled to the flyback transformer and the signal transformer. The secondary-side controller is configured at least to operate in a current control mode to cause a pulse width modulation (PWM) signal to be generated based on a set of parameters to control operation of the primary-side controller.

Abstract: Controlling an active clamp field effect transistor (FET) and a primary-side FET in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET and the primary-side FET across a same galvanic isolation barrier.

Abstract: A primary-side-controlled fly-back converter is provided to eliminate cross-conduction between a power-switch (PS) on a primary side and a synchronous-rectifier (SR) on a secondary side when operating in continuous conduction mode (CCM). Generally, the converter includes a transformer having a primary coupled to a rectified AC input through the PS, and a secondary coupled to a DC output through the SR, the SR having a drain coupled to the secondary winding. A fly-back-controller includes a primary-controller operable to control a duty cycle of the PS, and a secondary-controller operable to turn OFF the SR when the PS turns ON in CCM. The secondary-controller includes a CCM zero-crossing-detector comparator having a first input coupled to the drain of the SR through a capacitor, and is operable to detect a sharp change in a drain voltage when the PS turns ON during CCM, and to output a signal to turn OFF the SR.

Abstract: A fly-back converter and method of operating is provided to eliminate cross-conduction between a power-switch (PS) on a primary side of a transformer and a synchronous-rectifier (SR) on a secondary side when operating in continuous conduction mode. Generally, the method includes turning on the SR when a drain voltage of the SR drops to a negative voltage followed by a rise in the SR-drain-voltage at a first slope as a current is drawn from the secondary side of the transformer through the SR. When the PS is turned on before the transformer is completely discharged cross-conduction causes a change in the rise of the drain voltage to a second slope greater than the first slope. By turning off the SR within 50 ns of the change in the rise of the drain voltage, cross-conduction is minimized or eliminated without receiving turn-on information from a controller operating the PS.

Abstract: A Universal Serial Bus (USB) controller including a Vconn switch having a current controlled architecture, and method for operating the same, are described. In an example embodiment, the Vconn switch includes first and second transistors coupled in series between a Vconn terminal and a communication channel (CC) terminal, a replica switch coupled to the Vconn terminal, a replica current generator coupled to the replica switch, and a resistance control module coupled to the replica current generator. The replica current generator is operable to match a current through the replica switch to the current supplied to the CC terminal through the first and second transistors. The resistance control module is operable to use a digital output of a current inverter to control an in-rush current to the CC terminal.

Abstract: A secondary side controller for a flyback converter can include a synchronous rectifier (SR) gate driver pin coupled to a gate of an SR transistor on a secondary side of the flyback converter. An error amplifier is coupled to an output of a voltage bus of the flyback converter, the error amplifier to generate an error signal indicative of a voltage of the output of the voltage bus. Control logic is coupled to the error amplifier and to the SR transistor, the control logic to: detect when the voltage is at least a threshold percentage higher than a sink voltage required by a sink device coupled to the output of the voltage bus; detect assertion of a skip mode signal; and cause the SR transistor to be driven during a skip mode such as to partially discharge an output capacitor coupled to the output of the voltage bus.

Abstract: A secondary-side-controller for a QR flyback converter and method for operating the same are provided. Generally, the secondary-side-controller includes a driver configured to control a power-switch (PS) on a primary side of converter to turn on the PS when a sinusoidal input voltage to the converter is at one of a plurality of valleys, an analog-to-digital-converter (ADC) to read the input voltage, output voltage, and load current, and generate digital signals based thereon. A valley-controller coupled to the driver, ADC, a look-up-table and a pulse width modulator (PWM) receives the signals from the ADC and using the look-up-table determines at which valley of the plurality of valleys to couple a PWM signal from the PWM to the driver. The valley-controller is operable for each switching cycle of the PS to increment, decrement or leave unchanged the valley at which the PWM signal is coupled from the PWM to the driver.

Abstract: An AC-DC converter and method of operating the same is provided to sense negative voltage (NSN) on a synchronous rectifier (SR_DRAIN) on a secondary-side of the converter. The SR_DRAIN voltage is sensed and a first integration signal (volt-sec) generated based on a time and voltage for which the SR_DRAIN voltage is greater than a bus voltage (VBUS_IN) output from the secondary. When Volt-sec is greater than a reference voltage a volt-sec based NSN detect signal is generated. A second integration signal (integ_resetb) is generated based on the time for which the SR_DRAIN voltage is greater than VBUS_IN. A pulse width of integ_resetb is determined using a counter, and, when it exceeds a reference by a predetermined percentage, a counter-expiry signal is generated. The volt-sec based NSN detect signal and the counter-expiry signal are logically combined to generate a real NSN detect signal when one or both are present.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a method of operating a Universal Serial Bus Power Delivery (USB-PD) power converter is provided. The method includes generating a pulse width modulated (PWM) signal for controlling the power converter. An output current signal for the power converter is determined. The output current signal corresponds to an output current across an external sense resistor coupled in an output path of the USB-PD power converter. A fault condition is identified based on the PWM signal and the output current signal. Operation of the power converter is disabled responsive to identifying the fault condition.

Abstract: A gate driver circuit for a synchronous rectifier (SR) of a wireless power receiver (WPR) system includes: a first RC filter that outputs a delayed turn-on signal for a first high-side SR switch based on a signal input to the filter that indicates a zero-crossing condition for a coil current of the WPR system in a first direction; a second RC filter that outputs a delayed turn-on signal for a second high-side SR switch based on a signal input to the filter that indicates a zero-crossing condition for the coil current in the opposite direction; a first digital delay-and-hold circuit electrically connected to the output of the first RC filter and that stabilizes the delayed turn-on signal output by the first filter; and a second digital delay-and-hold circuit electrically connected to the output of the second RC filter and that stabilizes the delayed turn-on signal output by the second filter.

Abstract: A Universal Serial Bus controller including a Vconn switch having a current controlled architecture, and method for operating the same are provided. Generally, the Vconn switch includes first and second transistors coupled in series between a Vconn terminal and a communication channel (CC) terminal, a replica switch including a source coupled to the Vconn terminal, a replica current generator including a first input coupled to a drain of the replica switch and a second input coupled to a drain of the first transistor, and a resistance control module coupled to an output of the replica current generator and including an output coupled to a gate of the second transistor. The replica current generator is operable to match a current through the replica switch to that supplied through the first and second transistors to the CC terminal, and the resistance control module is operable to control resistance of the Vconn switch.

Abstract: An error amplifier includes an output pin coupled to a pulse width modulation (PWM) comparator of a buck-boost converter. A first transconductance amplifier adjusts an output current at the output pin and operates in a constant voltage mode. The first transconductance amplifier includes a first positive input to receive a first voltage reference and a first negative input coupled to a tap point of a voltage divider coupled between a voltage bus and a ground of the buck-boost converter. A second transconductance amplifier also adjusts the output current at the output pin and operates in a constant current mode. The second transconductance amplifier includes a second positive input to receive a second voltage reference and a second negative input coupled to a current sense amplifier, the current sense amplifier being coupled to a sense resistor positioned inline along the voltage bus.

Abstract: A method comprising controlling operation, by a secondary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a low-side field-effect transistor (FET). In response to controlling operation of the low-side FET, the method further includes triggering a zero-cross detection circuit. The method further includes measuring a first period of time between controlling operation of the low-side FET and triggering the zero-cross detection circuit. The method further includes measuring a second period of time between controlling operation of a high-side FET and triggering the zero-cross detection circuit. The method further includes adjusting a third period of time based on the first period of time and the second period of time, wherein the third period of time corresponds to a dead time between controlling operation of the high-side FET and the low-side FET.