Abstract: Techniques for avoiding false negative sense (NSN) detection in a flyback AC-DC converter are described herein. In an example embodiment, a secondary side controller of the AC-DC converter comprises a frequency detector, a negative sense detector, and control logic. The frequency detector is configured to determine a frequency of an input signal from the drain node of a synchronous rectifier (SR) circuit on the secondary side of the AC-DC converter. The negative sense detector is configured to determine a negative voltage of the input signal. The control logic is configured to: enable the negative sense detector, when the frequency of the input signal rises above a frequency threshold value; and turn on the SR circuit to transfer power to the secondary side of the AC-DC converter, when the negative voltage of the input signal falls below a voltage threshold value.

Abstract: A synchronous switching scheme with adaptive slew control in order to adiabatically charge and discharge a capacitor to recycle charge and generate a boosted voltage on the gate of the synchronous rectifier field effect transistor (FET) is described. In one embodiment, an apparatus includes a synchronous rectifier FET coupled to a transformer, and a secondary-side controller coupled to the synchronous rectifier FET. The secondary-side controller includes a synchronous rectifier gate driver (SRGD) coupled to a gate of the synchronous rectifier FET. The SRGD is to drive the synchronous rectifier FET using the capacitor and an adaptive slew rate, and to adiabatically charge and discharge the capacitor.

Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.

Abstract: Communicating fault indications between primary and secondary controller in a secondary-controlled flyback converter is described. In one embodiment, an apparatus includes a primary-side field effect transistor (FET) coupled to a flyback transformer coupled to the primary-side FET, and a primary-side controller coupled to the flyback transformer. The primary-side controller is configured to receive a signal from a secondary-side controller across a galvanic isolation barrier, apply a pulse signal to the primary-side FET in response to the signal to turn-on and turn-off the primary-side FET, communicate information to the secondary-side controller across the flyback transformer by varying a first pulse width of the pulse signal to a second pulse width and applying the pulse signal with the second pulse width to the primary-side FET.

Abstract: A secondary-side controller for an AC-DC converter that has a single synchronous rectifier sensing (SR_SNS) terminal, coupled to a synchronous rectifier (SR) of the AC-DC converter, and a voltage divider circuit coupled to the single SR_SNS terminal configured to provide signals to a sensing circuit. The voltage divider includes an active diode, an internal resistive element, and a switch, in which the active diode is configured to control the switch to enable or disable the internal resistive element based on a comparison result of a voltage at the single SR_SNS terminal and a reference voltage.

Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. In an example embodiment, an integrated circuit (IC) controller for the secondary side of the AC-DC converter comprises a zero-crossing detector (ZCD) block and a negative-sensing (NSN) block coupled to a terminal. The terminal is configured to receive an input signal from a drain node of a SR circuit on the secondary side of the AC-DC converter. The ZCD block is configured to determine when a voltage of the input signal reaches 0V. The NSN block is configured to determine a negative voltage of the input signal. An internal rectifier, coupled between the terminal and local ground, is configured to ensure that substantially no current flows through the terminal during operation of the ZCD block and the NSN block.

Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC) controller of the AC-DC converter includes a SR-SNS pin, a VBUS_IN pin, a first voltage-to-current converter, a sample-and-hold (S/H) circuit, a second voltage-to-current converter, and a signal generation circuit. The first voltage-to-current converter is coupled to remove a component of the output bus voltage sensed on the VBUS_IN pin from the voltage sensed on the SR-SNS pin. The S/H circuit is coupled to sample the voltage sensed on the SR-SNS pin and to provide a sampled voltage. The second voltage-to-current converter is coupled to convert the sampled voltage to a feed-forward current. The signal generation circuit is coupled to receive the feed-forward current and to generate feed-forward signals used to control operation of a primary side of the AC-DC converter.

Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. In an example embodiment, an integrated circuit (IC) controller for the secondary side of the AC-DC converter comprises a zero-crossing detector (ZCD) block and a negative-sensing (NSN) block coupled to a terminal. The terminal is configured to receive an input signal from a drain node of a SR circuit on the secondary side of the AC-DC converter. The ZCD block is configured to determine when a voltage of the input signal reaches 0V. The NSN block is configured to determine a negative voltage of the input signal. An internal rectifier, coupled between the terminal and local ground, is configured to ensure that substantially no current flows through the terminal during operation of the ZCD block and the NSN block.

Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side IC controller of the AC-DC converter includes a SR-SNS pin coupled to a peak-detector block, a zero-crossing block, and a calibration block. The calibration block is configured to: measure a loop turn-around delay (Tloop), a time (Tpkpk) between two successive peak voltages detected on the SR-SNS pin, and a time (Tzpk) from when the voltage sensed on the SR-SNS pin crosses zero voltage to when a peak voltage is detected on the SR-SNS pin; and set timing for a signal to turn on a power switch in a primary side of the AC-DC converter based at least on Tloop, Tpkpk, and Tzpk.

Abstract: Communicating fault indications between primary and secondary controller in a secondary-controlled flyback converter is described. In one embodiment, an apparatus includes a primary-side field effect transistor (FET) coupled to a flyback transformer coupled to the primary-side FET, and a primary-side controller coupled to the flyback transformer. The primary-side controller is configured to receive a signal from a secondary-side controller across a galvanic isolation barrier, apply a pulse signal to the primary-side FET in response to the signal to turn-on and turn-off the primary-side FET, communicate information to the secondary-side controller across the flyback transformer by varying a first pulse width of the pulse signal to a second pulse width and applying the pulse signal with the second pulse width to the primary-side FET.

Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC controller of the AC-DC converter includes a peak-detector block coupled to detect peak voltages sensed on a SR-SNS pin. The peak-detector block comprises a peak comparator, a sample-and-hold (S/H) circuit, and a DC offset circuit. The peak comparator is coupled to receive a sinusoidal input from the SR-SNS pin. The S/H circuit is coupled to sample the sinusoidal input and to provide a peak sampled voltage. The DC offset voltage circuit is coupled between the output of the S/H circuit and a reference voltage input of the peak comparator to subtract a DC offset voltage from the peak sampled voltage.

Abstract: An electronic device includes a first switch configured to connect a VCONN supply terminal of a Universal Serial Bus Type-C (USB-C) controller to a first configuration channel (CC) terminal of the USB-C controller in response to a USB-C connector being in a first orientation. A first current may flow through the first switch. The electronic device also includes an overcurrent component coupled to the first switch. The overcurrent component includes a second switch associated with the first switch. The second switch has a second current associated with the first current. The overcurrent component is configured to determine whether the first current is greater than a threshold current based on the first current and the second current. The overcurrent component is also configured to close the first switch in response to determining that the first current is greater than the threshold current.

Abstract: An example electronic device includes a first switch and a second switch that are each coupled to an overvoltage detection and protection circuit. The first switch is configured to connect a first sideband use (SBU) terminal of a Universal Serial Bus Type-C (USB-C) controller to a SBU crossbar switch of the USB-C controller. The second switch is configured to connect a second SBU terminal of the USB-C controller to the SBU crossbar switch. The overvoltage detection and protection circuit is configured to deactivate the first switch or the second switch when a voltage exceeding a predetermined threshold is detected on a terminal of the first switch or the second switch.

Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.

Abstract: A secondary side controller for an AC-DC converter and method for operating the same are provided. Generally, the controller includes a single synchronous rectifier sense (SR-SNS) pin coupled to a drain of a SR on a secondary of a transformer to sense a voltage (VSRD). In feed-forward (FF) mode VSRD is a sum of a voltage (VIN) on a primary divided by a turn-ratio (N) of the transformer and an output bus voltage (VBUS). A voltage-to-current (V2I) converter coupled to the SR-SNS pin and to the output bus removes VBUS from VSRD. A sample and hold (S/H) module coupled to the SR-SNS pin samples a voltage (VSAMP) including information on VIN/N. A VIN/N V2I converter coupled to the S/H module converts VSAMP to a feed-forward current (IFF), and a cancellation and signal module coupled thereto extracts information on VIN from IFF and generates signals to control the AC-DC converter.

Abstract: A flyback converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided. Generally, the secondary side controller includes an integrated circuit (IC) including a single SR-SNS pin coupled to a drain of a SR on a secondary side of the converter to sense a voltage on the drain, and a power switch (PS) drive pin coupled to a PS on a primary side to turn on the PS in response to a number of measurements based on the voltage sensed on the drain of the SR. The IC includes a calibration block to measure a loop turn-around delay, valley delays with respect to zero-crossing and set timing for a signal to turn on the PS in response to the voltage sensed on the drain of the SR at or very close the primary side valley improving efficiency and performance of the converter.

Abstract: An AC-DC converter with secondary side controller and synchronous rectifier (SR) architecture and method for operating the same are provided. Generally, the controller is implemented as an integrated circuit including a peak-detector module having a peak comparator with a first input coupled to a drain of the SR through a single SR sense (SR-SNS) pin to receive a sinusoidal input. A sample and hold (S/H) circuit with an input coupled to the SR-SNS pin samples the sinusoidal input and holds on an output of thereof a peak sampled voltage received on the input. A direct current (DC) offset voltage coupled between the output of the S/H circuit and the second input of the peak comparator subtracts an DC offset voltage from the peak sampled voltage to compensate for DC offset inaccuracies introduced by the S/H circuit and the peak comparator. Other embodiments are also disclosed.

Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. Generally, the secondary side controller includes a zero-crossing detector block, a negative-sensing block, a peak-detector block and a line-feed-forward block integrated in an integrated circuit (IC), and coupled to a secondary side of the converter through a single SR-sense (SR_SNS) pin through which the IC is coupled to a drain of the SR. The single SR_SNS pin has a maximum input voltage less than a rectified AC input voltage input to a secondary side of the converter, and, in one embodiment, is coupled to the drain of the SR through a voltage divider circuit including circuit elements both internal and external to the IC along with a rectifier element in series with the internal resistor.

Abstract: A USB-C controller, disposed on an integrated circuit (IC), comprises a first pair of terminals to communicate with a first communication protocol that is other than USB, a second pair of terminals to communicate with a second communication protocol that is other than USB, and a third pair of terminals, each of which is to be coupled to a corresponding SBU1 terminal or SBU2 terminal of a Type-C receptacle. The USB-C controller further includes: a multiplexer to selectively couple the first pair of terminals to the third pair of terminals and the second pair of terminals to the third pair of terminals: and logic to control the multiplexer according to a mode enabled within a configuration channel (CC) signal.

Abstract: A system includes a power switch configured to receive a voltage on a first terminal. The first terminal is coupled to a voltage regulator. The power switch is also configured to provide the voltage to a second terminal. The second terminal is coupled to a VBUS terminal of a Universal Serial Bus Type-C (USB-C) connector. The system also includes a USB controller coupled to the power switch and to the first terminal and the second terminal. The the USB controller is configured to detect a first voltage at the first terminal and to detect a second voltage at the second terminal. The USB controller is configured to adjust operation of the power switch in response to determining that the second voltage is above a particular voltage or within a particular voltage range.