Patents by Inventor Arvind Kumar

Arvind Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250192557
    Abstract: A method for mitigating sub-synchronous power oscillations in an inverter-based resource connected to an electrical grid via a series-compensated grid connection includes determining, via a controller, one or more rotor current commands for a power converter of the inverter-based resource. The method also includes applying, via a software module of the controller, at least one stator current component to the one or more rotor current commands to provide active damping to mitigate the sub-synchronous power oscillations in the inverter-based resource. Further, the method includes determining, via the controller, at least one voltage command for the inverter-based resource as a function of the one or more rotor current commands and the at least one stator current component. Moreover, the method includes controlling, via the controller, the inverter-based resource, based at least in part, on the voltage command.
    Type: Application
    Filed: March 15, 2022
    Publication date: June 12, 2025
    Inventors: Rabisankar Roy, Veena Padmarao, Subbarao Tatikonda, Rupam Basak, Arvind Kumar Tiwari
  • Patent number: 12301011
    Abstract: A method and system for controlling a hybrid power generation plant by receiving from a grid a data from among a power demand, a peak hour, a frequency, a ramp, a reactive power, or a voltage. A power production of power sources in the plant is varied depending on the received data and a characteristic of each of the power sources. The varying increases an active power produced by the plant while maintaining reactive power at a constant level by increasing a real power of a first power source while decreasing a reactive power produced by the first power source and simultaneously increasing a reactive power produced by a second power source without increasing a real power produced by the second power source. The first power source is a different type of power source from the second power source.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: May 13, 2025
    Assignee: GE Renewable Technologies
    Inventors: Veena Padmarao, Raganathan Radhakrishnan Nair, Arvind Kumar Tiwari, Santhosh Kumar C, José Luis Ferral
  • Patent number: 12300577
    Abstract: An exemplary apparatus includes a substrate; a plurality of chips mounted onto the substrate; a plurality of cold plates corresponding to the plurality of chips; means for pressing each of the cold plates toward a corresponding one of the chips; means for delivering coolant flow to the cold plates; and means for adjusting the cooling power of the plurality of cold plates, responsive to at least one sensed parameter of the plurality of chips.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: May 13, 2025
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Chainer, Todd Edward Takken, Joshua M. Rubin, Arvind Kumar
  • Patent number: 12301005
    Abstract: A method for controlling an active harmonic filter of an inverter-based resource includes receiving, via a maximum compensation tracker module, a grid feedback signal, determining, via the maximum compensation tracker module, a phase shift signal based, at least in part, on the grid feedback signal, applying, via the maximum compensation tracker module, a phase shift offset signal to the phase shift signal to obtain a modified phase shift signal, determining, via the maximum compensation tracker module, a voltage reference signal for the active harmonic filter based, at least in part, on the grid feedback signal and the modified phase shift signal; and controlling, via the maximum compensation tracker module, the active harmonic filter using the voltage reference signal, wherein the phase shift offset signal ensures that the active harmonic filter injects a current substantially out of phase of a targeted harmonic.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: May 13, 2025
    Assignee: GE Vernova Infrastructure Technology LLC
    Inventors: Pushkar Chandrakant Chaudhari, Kapil Jha, Robert Gregory Wagoner, Werner Gerhard Barton, Saurabh Shukla, Arvind Kumar Tiwari
  • Publication number: 20250144267
    Abstract: [Problem] To provide an additional use of a polysaccharide derivative such as a tissue adhesive material [Solution] According to some embodiments, a tissue adhesive material is provided, which is intended to be used for a hard and thick tissue and/or a connective tissue and comprises a polysaccharide derivative having such a structure that a group represented by formula (A) is introduced in an acidic, basic or amphoteric polysaccharide.
    Type: Application
    Filed: February 16, 2022
    Publication date: May 8, 2025
    Applicants: MOCHIDA PHARMACEUTICAL CO., LTD., THE UNIVERSITY OF TOKYO
    Inventors: Taichi ITO, Arvind Kumar Singh CHANDEL, Mitsuko ISAJI
  • Publication number: 20250142911
    Abstract: Embodiments of the present disclosure generally relate to epitaxial film stacks and vapor deposition processes for preparing the epitaxial film stacks. In one or more embodiments, a carbon-doped silicon-germanium and silicon mini-stack is produced with relatively low defects or crystal imperfections. A multi-layered epitaxial stack containing a plurality of the carbon-doped silicon-germanium and silicon mini-stacks is deposited on a substrate. Each multi-layered epitaxial stack contains a carbon-doped silicon germanium stack and a silicon film. The carbon-doped silicon germanium stack contains a carbon-silicon-germanium layer disposed between a first silicon-germanium layer and a second silicon-germanium layer. The silicon film contains the silicon bulk layer disposed on the silicon seed layer.
    Type: Application
    Filed: September 18, 2024
    Publication date: May 1, 2025
    Inventors: Arvind KUMAR, Roya BAGHI, Mahendra PAKALA, Thomas KIRSCHENHEITER
  • Publication number: 20250120913
    Abstract: A pharmaceutical composition of Quercetin nanosuspension comprising Quercetin dihydrate, about 0.1% w/w to 10% w/w of Poloxamer, about 0.1% w/w to 10% w/w of polyvinyl pyrrolidone, and about 0.1% w/w to 10% w/w of polyethylene glycol. A method for preparing Quercetin nanosuspension, comprising the steps of dissolving polyvinyl pyrrolidone, Poloxamer, and polyethylene glycol in purified water, adding Quercetin to the above solution, subjecting the resulting mixture to bead milling to form Quercetin nanocrystals or nanosuspension.
    Type: Application
    Filed: October 11, 2024
    Publication date: April 17, 2025
    Inventors: Arvind Kumar BANSAL, Shailja DIXIT, Jean Pierre LEHNER, Maurice SOFEIR
  • Publication number: 20250125842
    Abstract: Systems and methods described provide a multiple-input multiple-output (MIMO) optimization service. A network device in a RAN predicts high usage thresholds and available per-service resources for supporting MIMO transmissions. The network device identifies, based on the predicted usage thresholds, user equipment (UE) devices that have a high-throughput session and have high usage levels on a cell. The network device assigns, based on the predicted available per-service resources, sounding reference signal (SRS)-based MIMO resources to the UE devices in the cell and assigns codebook-based MIMO resources to other UE devices in the cell.
    Type: Application
    Filed: October 11, 2023
    Publication date: April 17, 2025
    Inventors: Arvind Kumar, Sachin Vargantwar
  • Patent number: 12272426
    Abstract: Methods and apparatus for duty cycle adjuster optimization training algorithms to minimize jitter associated with DDR5 DRAM transmitters. Basic and Advanced Duty Cycle Adjuster (DCA) training algorithms are implemented to reduce duty cycle error and hence reduce phase mismatch translated jitter in the transmitter DQS signals. In accordance with aspects of the Basic DCA training algorithm, duty cycles for QCLK, IBQCLK, and QBCLK are adjusted by a memory controller that utilizes a DCA function implemented on a memory module (e.g., DDR5 SDRAM DIMM) to obtain a first set of optimized DCA code settings. The first set of optimized DCA code settings are then used as initial settings for the Advance DCA training algorithm to further optimize the DCA code settings for QCLK, IBQCLK, and QBCLK. A similar technical may be employed to reduce duty cycle error and jitter for DQ signals.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: April 8, 2025
    Assignee: Intel Corporation
    Inventors: Arvind Kumar, Dean-Dexter R. Eugenio, Santhosh Muskula
  • Publication number: 20250107969
    Abstract: A vial adapter includes a body having a component connection interface, a piercing member having a first end connected to the body and a second end positioned opposite the first end, with the piercing member and the body defining a fluid passageway in fluid communication with the component connection interface, and a vial securing member extending from the body. The vial securing member is configured to secure the body to a vial. The vial securing member is moveable between a first position where the vial securing member defines a first length and a first width and a second position where the vial securing member has a second length and a second width, where the first length is larger than the first width, the first length is larger than the second length, and the second width is larger than the first width.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Erik Rundlett, Narsi Reddy Sanikommu, Prashant Dalavi, Arvind Kumar Mishra, Akash Kaloji
  • Publication number: 20250085932
    Abstract: Systems, computer program products, and methods for interactive automated code generation and modification for data processing are provided. The method includes causing a rendering of a flow designer interface including a flow portion and a plugin portion. The plugin portion includes engageable plugin icon(s) corresponding to one or more plugins. The method also includes receiving a first plugin input based on engagement of a first plugin icon. The first plugin input is a selection of a first plugin. The method further includes causing a rendering of a representation of the first plugin on the flow portion. The method further includes receiving a second plugin input based on engagement of a second plugin icon. The method also includes causing a rendering of a representation of the second plugin on the flow portion. The method also includes generating a flow operation based on the flow portion of the flow designer interface.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Ganesh Agrawal, Suresh Solomon, Rajneesh Acharya, Rakesh Shah, Vikash Agarwal, Mark Labbancz, Deepak Chandrasheker Kundapur, Rahul Tandon, Laura A. Bertarelli Hamilton, Akhil Sunil Kudal, Manoj Narayanan, Mohal Mukundbhai Sayani, Anju Jha, Dharanitharan Sukumar, Rakeshkumar Prajapati, Shubhro Protim Ghosh, Arvind Kumar Rai
  • Publication number: 20250080590
    Abstract: A method for exchanging outbound registration count information among I-CSCFs and using the outbound registration count information for S-CSCF selection includes receiving, at a first I-CSCF of a cluster of I-CSCFs and from each S-CSCF in a cluster of S-CSCFs, a value indicating a registration capacity of the S-CSCF. The method further includes receiving, at the first I-CSCF and from at least one other I-CSCF in the cluster of I-CSCFs, outbound registration counts indicating numbers of outbound registrations that the at least one other I-CSCF has with the S-CSCFs in the cluster of S-CSCFs. The method further includes calculating, by the first I-CSCF and using the values indicating the registration capacities of the S-CSCFs and the outbound registration counts, values indicating updated registration capacities of the S-CSCFs. The method further includes using, by the first I-CSCF, the values indicating the updated registration capacities to select an S-CSCF for at least one outbound registration message.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Inventors: Arvind Kumar Singh, Agnivesh Kumpati
  • Patent number: 12241628
    Abstract: A swirler assembly for a combustor includes at least one swirler including a plurality of swirl vanes arrayed about an axis of the swirler. The plurality of swirl vanes includes a first ring of first sub-vanes and a second ring of second sub-vanes, the first ring of first sub-vanes and the second ring of second sub-vanes being separated by a gap therebetween.
    Type: Grant
    Filed: September 1, 2023
    Date of Patent: March 4, 2025
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Gurunath Gandikota, Karthikeyan Sampath, Perumallu Vukanti, Allen M. Danis, Scott M. Bush, Steven Clayton Vise, Hari Ravi Chandra, Rimple Rangrej, Saket Singh, Pradeep Naik, Neeraj Kumar Mishra, Arvind Kumar Rao, Balasubramaniam Venkatanarayanan, Ranjeet Kumar Mishra
  • Publication number: 20250034218
    Abstract: Provided are engineered polypeptides including CAP18 variants, and other engineered cathelicidin polypeptides based on BMAP28, BAC7, K9CATH and PMAP36. Also provided are methods for inhibiting growth of at least one methanogen in an animal. Further provided are methods of reducing greenhouse gas emissions, such as methane emissions, that use such compositions. The compositions and methods include one or more of the antimicrobial peptides including CAP 18 variants and other engineered cathelicidin polypeptides based on BMAP28, BAC7, K9CATH and PMAP36.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 30, 2025
    Inventors: Dwi Susanti, Arvind Kumar, Dharanesh Mahimapura Gangaiah
  • Patent number: 12210604
    Abstract: Systems and methods for multi-modal user device authentication are disclosed. An example electronic device includes a first sensor, a microphone, a first camera, and a confidence analyzer to authenticate a subject as the authorized user in response to a user presence detection analyzer detecting a presence of the subject and one or more of (a) an audio data analyzer detecting a voice of an authorized user or (b) an image data analyzer detecting a feature of the authorized user. The example electronic device includes a processor to cause the electronic device to move from a first power state to a second power state in response to the confidence analyzer authenticating the user as the authorized user. The electronic device is to consume a greater amount of power in the second power state than the first power state.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: January 28, 2025
    Assignee: Intel Corporation
    Inventors: Aleksander Magi, Barnes Cooper, Arvind Kumar, Julio Zamora Esquivel, Vivek Paranjape, William Lewis, Marko Bartscherer, Giuseppe Raffa
  • Publication number: 20250030688
    Abstract: A method for admitting an entity computing device to a network includes receiving, by a network computing device, a request from an entity computing device for admission to a network and the network computing device determining whether a signal strength associated with the entity computing device satisfies a signal strength threshold value. In response to determining the signal strength associated with the entity computing device satisfies the signal strength threshold value, the network computing device determines whether one or more network conditions associated with the network are satisfied, and in response to determining the one or more network conditions associated with the network are satisfied, the network computing device admits the entity computing device to the network.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 23, 2025
    Inventors: Muhib T. Oduwaiye, Ravi Kiran Gundu, Arvind Kumar Kopparapu
  • Patent number: 12204751
    Abstract: In a memory system, reference voltage training per path provides the capability to train receiver and transmitter reference voltages to optimal values based on selected feedback per path from the memory device. Training receiver reference voltages to an optimal receiver reference voltage per path includes programming dedicated mode registers that enable a local receiver voltage reference adjuster circuit to adjust the receiver reference voltage per path to the optimal receiver reference voltage per path. Transmitter reference voltage training includes the capability to also train an optimal input timing delay for an optimal transmitter reference voltage. Reference voltage training can be performed by a host component and/or a test system having access to the selected feedback per path of the memory device undergoing training.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: January 21, 2025
    Assignee: Intel Corporation
    Inventors: Arvind Kumar, Dean-Dexter R. Eugenio, John R. Goles, Santhosh Muskula
  • Publication number: 20250022800
    Abstract: A 3D chip (or wafer) stack is provided in which a customized redistribution layer is located between each semiconductor wafer of the chip (or wafer) stack. The customized redistribution layer connects functional die sites on a first semiconductor wafer to functional die sites on a second semiconductor wafer, while by-passing non-functional die sites on the second semiconductor wafer.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Timothy J. Chainer, Joshua M. Rubin, John W. Golz, Mounir Meghelli, Todd Edward Takken, Arvind Kumar
  • Publication number: 20250020565
    Abstract: The present invention relates to a permeation test cell for permeation testing of materials against chemicals. The permeation test cell comprises an upper body provided with first vents and a lower body provided with second vents, for passing a first and a second gaseous stream. A perforated Polytetrafluoroethylene (PTFE) grid on the sample support plate is placed underneath the test sample to allow passage of the contaminant to the sorbent tube. A test sample with a contaminant is disposed in the permeation test cell. The second vent is configured to be attached to a sorbent tube for accumulation of contaminant permeating through the test sample. The permeation test cell is configured to receive a weight on the test sample for forcing permeation of the contaminant through the test sample.
    Type: Application
    Filed: November 3, 2022
    Publication date: January 16, 2025
    Inventors: Prabhat Garg, Mohammad Imran, Vikas Baburao Thakare, Atul Kumar Sonkar, Arvind Kumar Gupta
  • Publication number: 20250024485
    Abstract: In some implementations, a distributed unit (DU) associated with a network node may determine a rate variation associated with one or more of a quality of service (QOS) flow or a network slice. The DU may perform a scheduling for a user equipment (UE) based on the rate variation, wherein the scheduling is associated with an adjusted data rate based on the rate variation.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 16, 2025
    Applicant: Verizon Patent and Licensing Inc.
    Inventors: Jin YANG, John J. COOKE, Susan Wu SANDERS, Arvind KUMAR