Patents by Inventor Arvind Kumar

Arvind Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210309641
    Abstract: Compounds and methods for the treatment of a bacterial infection or the potentiation of an antibiotic in treating a bacterial infection are described herein.
    Type: Application
    Filed: June 13, 2019
    Publication date: October 7, 2021
    Applicant: GEORGIA STATE UNIVERSITY RESEARCH FOUNDATION, INC.
    Inventors: Binghe Wang, David W. Boykin, Manjusha Roy Choudhury, Arvind Kumar, Bingchen Yu, Mengyuan Zhu
  • Publication number: 20210313391
    Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Arvind Kumar, Joshua M. Rubin
  • Publication number: 20210312972
    Abstract: A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 7, 2021
    Inventors: Arvind A. Kumar, James Alexander McCall, Bill H. Nale, John R. Goles, Dean-Dexter R. Eugenio
  • Patent number: 11133259
    Abstract: A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Rubin, Arvind Kumar, Lawrence A. Clevenger, Steven Lorenz Wright, Wiren Dale Becker, Xiao Hu Liu
  • Publication number: 20210296898
    Abstract: A system for controlling a hybrid power generation plant is provided. The system is programmed to receive current conditions at the plurality of power generating assets including a first asset type and a second asset type, determine a forecast for a period of time based at least in part on the current conditions, determine that a first asset of the first asset type of the plurality of power generating assets has an available uprate margin for production of a first amount of active power, determine that a second asset of the second asset type of the plurality of power generating assets has capacity to generate a second amount of reactive power, instruct the first asset to reduce production of reactive power by the second amount and increase production of active power by the first amount, and instruct the second asset to increase production of reactive power by the second amount.
    Type: Application
    Filed: March 19, 2020
    Publication date: September 23, 2021
    Inventors: Veena Padmarao, Arvind Kumar Tiwari, Aditya Vyas, Karen Emanuelle Hernandez Pagan
  • Publication number: 20210294969
    Abstract: One embodiment provides a method, including: obtaining a plurality of previously submitted application documents, wherein each of the previously submitted application documents comprises information provided by a user who initiated a given previously submitted application document; clustering the plurality of previously submitted application documents into clusters of application documents based upon topics of the previously submitted application documents; selecting a representative application document; identifying entities contained within a given representative application document, wherein each of the entities corresponds to information to be entered into a new application document created from the given representative application document; and engaging in a dialogue with a user to create the new application document utilizing a similar representative application document to request information from the user, wherein the similar representative application document comprises a representative application d
    Type: Application
    Filed: March 19, 2020
    Publication date: September 23, 2021
    Inventors: Balaji Viswanathan, Ajay Gupta, Harshit Kumar, Arvind Agarwal
  • Patent number: 11126235
    Abstract: A first apparatus is disclosed, including: a detection circuitry to detect a first voltage level of reference current received from a second apparatus, where the second apparatus is to provide the reference current at a second voltage level; and a controller to negotiate a power transmission agreement with the second apparatus for transmission of power from the second apparatus to the first apparatus, based at least in part on a difference between the first voltage level and the second voltage level.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Jagadish Vasudeva Singh, Tarakesava Reddy Koki, Arvind Sundaram, Vinaya Kumar Chandrasekhara
  • Patent number: 11127325
    Abstract: Technologies for performing a simplified pixel shifting scheme on a display (e.g., an organic light emitting diode (OLED) display) are disclosed herein. An electronic device presents, on the display, a virtual display having an active area and a margin area surrounding the active area. The active area is to display content (e.g., image data, video data, etc.), and an amount of pixels in the virtual display is greater than an amount of pixels in the active area. The electronic device is also to shift the pixels of the active area within the virtual display according to a pixel shifting technique and update a touch coordinate offset for the touch screen interface based on the shift.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Zhiming Zhuang, Jun Jiang, Arvind Kumar
  • Patent number: 11114963
    Abstract: A power generation system (100, 200, 300, 400) is presented. The power generation system includes a prime mover (102), a doubly-fed induction generator (DFIG) (104) having a rotor winding (126) and a stator winding (122), a rotor-side converter (106), a line-side converter (108), and a secondary power source (110, 401) electrically coupled to a DC-link (128). Additionally, the power generation system includes a control sub-system (112, 212, 312) having a controller, and a plurality of switching elements (130, and 132 or 201). The controller is configured to selectively control switching of one or more switching elements (130, and 132 or 201) based on a value of an operating parameter corresponding to at least one of the prime mover, the DFIG, or the secondary power source to connect the rotor-side converter in parallel to the line-side converter to increase an electrical power production by the power generation system.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 7, 2021
    Assignee: General Electric Company
    Inventors: Govardhan Ganireddy, Arvind Kumar Tiwari, Yashomani Y Kolhatkar, Anthony Michael Klodowski, John Leo Bollenbecker, Harold Robert Schnetzka, Robert Gregory Wagoner, Veena Padmarao
  • Publication number: 20210272402
    Abstract: A method can include obtaining access code data corresponding to an access code transmitted to a user device. The method can further include monitoring the user device. The method can further include determining, based on the monitoring, that the access code is shared. The method can further include initiating, in response to the determining that the access code is shared, an invalidation of the access code.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Inventors: Saurabh Yadav, Raghuveer Prasad Nagar, Arvind Kumar
  • Patent number: 11101357
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 24, 2021
    Assignee: Tessera, Inc.
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • Patent number: 11101318
    Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: August 24, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arvind Kumar, Joshua M. Rubin
  • Publication number: 20210248072
    Abstract: Various embodiments are provided for optimized placement of data structures in a hierarchy of memory in a computing environment. One or more data structures may be placed in a first scratchpad memory, a second scratchpad memory, an external memory, or a combination thereof in the hierarchy of memory according to a total memory capacity and bandwidth, a level of reuse of the one or more data structures, a number of operations that use each of the one or more data structures, a required duration each the one or more data structures are required to be placed a first scratchpad or a second scratchpad, and characteristics of those of the one or more data structures competing for placement in the hierarchy of memory that are able to co-exist at a same time step. The second scratchpad memory is positioned between the external memory and the first scratchpad memory at one or more intermediary layers.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arvind KUMAR, Swagath VENKATARAMANI, Ching-Tzu CHEN
  • Publication number: 20210247919
    Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.
    Type: Application
    Filed: April 2, 2021
    Publication date: August 12, 2021
    Inventors: Dean-Dexter R. EUGENIO, Arvind KUMAR, John R. GOLES, Christopher E. COX
  • Patent number: 11088310
    Abstract: On a first superconducting layer deposited on a first surface of a substrate, a first component of a resonator is pattered. On a second superconducting layer deposited on a second surface of the substrate, a second component of the resonator is patterned. The first surface and the second surface are disposed relative to each other in a non-co-planar disposition. In the substrate, a recess is created, the recess extending from the first superconducting layer to the second superconducting layer. On an inner surface of the recess, a third superconducting layer is deposited, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer. Excess material of the third superconducting layer is removed from the first surface and the second surface, forming a completed through-silicon via (TSV).
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua M. Rubin, Jared Barney Hertzberg, Sami Rosenblatt, Vivekananda P. Adiga, Markus Brink, Arvind Kumar
  • Publication number: 20210241261
    Abstract: A method and system to reduce card transaction fee while enabling the payment from dynamically mapped retail cards. Being a mapping and API based solution, technical integration with any bank is much easier with very less cost while enabling the easy future enhancements. With this Solution customer will map all his retail card to any one credit card on app and while making the payments solutions will enable bank to take payment from the respective retail card for retailer. With this mapping-based solution customer will get same functionality, if due to any reason he is not able to use his mobile for payment and use the credit card mapped.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 5, 2021
    Inventors: ARVIND KUMAR, Bibhupriya Acharya
  • Patent number: 11075545
    Abstract: A wireless power transfer system is disclosed. The wireless power transfer system includes a first converting unit for converting a first DC voltage of an input power to a first AC voltage, a contactless power transfer unit for transmitting the input power having the first AC voltage, and a second converting unit for transmitting the power having a second DC voltage corresponding to the first AC voltage to an electric load. Additionally, the wireless power transfer system includes an active voltage tuning unit for controlling the second DC voltage based on a difference between the second DC voltage and a reference voltage and at least one among a difference between the resonant frequency and the constant operating frequency and a difference between a phase angle of the first AC voltage and a phase angle of an AC current.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 27, 2021
    Assignee: General Electric Company
    Inventors: Kapil Jha, Arun Kumar Raghunathan, Arvind Kumar Tiwari, Deepak Aravind
  • Patent number: 11074268
    Abstract: The embodiments herein relate to operational data analysis (ODA) and, more particularly to automate operational data analysis and generate the analysis report for various products using a web-based multi-tenant product intelligence framework. The system allows the user to configure a data collection process, define schema structure, select a data storage for storing the collected data, select or create a data formatting algorithm, and generate a data report to perform the ODA process. Based on the ODA report, appropriate decisions can be taken by an organization.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: July 27, 2021
    Assignee: HCL TECHNOLOGIES LTD
    Inventors: Arvind Kumar Maurya, Dhanyamraju S U M Prasad, Yogesh Gupta, Ravi Prasad, Karuna Sharma
  • Publication number: 20210224900
    Abstract: A method and product designed for preferably creating, validating and executing regression based models and calculations for Stress Testing and Entity Planning purposes is provided covering model execution life-cycle details from model creation, validation, and execution. The preferred embodiments include a self-service regression based model configuration and creation with workflow approval tool called a model wizard; a central standardized I/O data interface called ODS to receive and store quarterly historical and spot financial market information, and reference data used as model input, and to store model output(s) in the preferred form of quarterly base and stress projections; a java based execution engine to run the approved models from the repository with ability to apply model adjustments; a web-based user interface to view the model lineage, input, equations in mathematical form using MathJax and the output.
    Type: Application
    Filed: April 2, 2021
    Publication date: July 22, 2021
    Inventors: KRESIMIR MARUSIC, Arvind Kumar Rai, Bharat Gopalan, Young Been Eom, Dwight Silvera, Brandon Von-Feldt, Monojit Mitra, Laura Bertarelli, Rajneesh Acharya, Seth Lipschitz, Jason Lin, Patricia M. Gavin, Ronakkumar S. Patel
  • Publication number: 20210224275
    Abstract: Techniques are described herein for leveraging recurrent neural networks for query processing. In some embodiments, a query analytic system determines a sequence of tokens for at least a portion of a query and determines a vector representation for each token. The query analytic system further generates, using a neural network based on the sequence of tokens, a performance prediction associated with executing at least the portion of the query, wherein the neural network assigns at least a first weight for at least a first token in the sequence of tokens based at least in part on at least a second token that preceded the token in the sequence. The query analytic system further triggers a responsive action, such as triggering an alert and/or tuning the query, based at least in part on the performance prediction.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Applicant: Oracle International Corporation
    Inventors: Arvind Kumar Maheshwari, Vamshidhar Reddy Pasham, Shantanu Mahajan, Debottam Kundu