Abstract: A method, a network device, and a non-transitory computer-readable storage medium are described in relation to a reestablishment connectivity service. The reestablishment connectivity service may include generating and providing minimum receive level cell information used only for reestablishment by end devices. The minimum receive level cell information may include a minimum receive level value, such as a qRXLevMin value associated with a cell selection criterion. The minimum receive level cell information may include correlated data, such as a Fifth Generation Quality of Service Identifier (5QI) value, an application service identifier, a category of an application service, or a traffic characteristic value. The minimum receive level value may differ from a minimum receive level value for non-reestablishment by end devices.

Abstract: The present invention provides probiotic compositions and methods for improving animal health. The probiotic compositions include one or more isolated strains of Lactobacillus reuteri which colonizes the gastrointestinal tract to increase the health of an animal, including to alleviate the effects of chronic alcohol consumption, leaky gut, increased intestinal permeability and inflammation and treat or prevent alcohol-associated intestinal dysbiosis, leaky gut, increased intestinal permeability and inflammation, including intestinal inflammation associated with inflammatory bowel disease.

Abstract: Systems and methods for multi-modal user device authentication are disclosed. An example electronic device includes a first sensor, a microphone, a first camera, and a confidence analyzer to authenticate a subject as the authorized user in response to a user presence detection analyzer detecting a presence of the subject and one or more of (a) an audio data analyzer detecting a voice of an authorized user or (b) an image data analyzer detecting a feature of the authorized user. The example electronic device includes a processor to cause the electronic device to move from a first power state to a second power state in response to the confidence analyzer authenticating the user as the authorized user. The electronic device is to consume a greater amount of power in the second power state than the first power state.

Abstract: Exemplary semiconductor processing methods may include forming a barrier layer on a first source/drain material disposed on a substrate housed within a processing region of a semiconductor processing chamber. The first source/drain material may be doped with a dopant. The methods may include growing an epitaxial silicon-containing material on the barrier layer. The barrier layer may reduce an amount of diffusion of the dopant from the first source/drain material into the epitaxial silicon-containing material.

Abstract: The present invention relates to efficient delivery of anti-infective activity, immunomodulatory factors, or growth-promoting biomolecules directly to the digestive tract of an animal via a live delivery platform. The live delivery platform can be a genetically modified microorganism. Delivery can be accomplished with a Lactobacillus sp which colonizes the gastrointestinal tract. The anti-infective activity can be a bacteriocidal or bacteriostatic peptide, an antibody or fragment thereof which specifically recognizes a pathogen, or a phage, or a lytic peptide from a phage which specifically targets a certain pathogen.

Abstract: An integrated circuit includes a host die and a base die, both of which are disposed on an interposer. The host die includes multiple processors, and the base die includes at least two high-bandwidth memory (HBM) stacks that are disposed on the base die and communicate with the host die through the base die and the interposer. The at least two HBM stacks and the host die are arranged in a row with the host die at one end of the row. The base die further includes compute circuitry to receive data from one or both of the HBM stacks and to execute instructions received from the host die. At least a portion of the compute circuitry is disposed on the base die between the two HBM stacks.

Abstract: Compounds and methods for the treatment of a bacterial infection or the potentiation of an antibiotic in treating a bacterial infection are described herein.

Abstract: A memory controller in an integrated circuit system includes a receiver circuit that performs oversampling in time and voltage. The receiver circuit receives a data signal with pulse amplitude modulation (PAM) having N signal levels from a memory module over a data lane, N > 2. The receiver circuit generates K samples by sampling the data signal at a sequence of time points in a unit time interval. The receiver circuit uses R voltage comparator blocks to generate R signal level estimates from the same sample out of the K samples. The voltage comparator blocks compare the same sample against (N-1) voltage thresholds with different offsets configured for different voltage comparator blocks. The receiver circuit identifies one of the N signal levels to which the data signal is mapped based on all signal level estimates generated from the K samples, and outputs a symbol corresponding to the identified signal level.

Abstract: A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives from a processor a bit stream including a given symbol to be transmitted according to pulse-amplitude-modulation (PAM) with N signal levels on a first lane of multiple lanes. The lanes connect the transmitter module to a memory module in the integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk from other lanes on the first lane. The parameters are identified based on a pending transition in signal levels in each of the other lanes. The transmitter module superposes the parameters of the other lanes on the given symbol to adjust the given symbol on the first lane. A digital-to-analog converter (DAC) on the first lane generates an analog output to the memory module. The analog output represents the adjusted given symbol.

Abstract: A memory controller in an integrated circuit system performs bi-directional data transfer at a clock frequency between the memory controller and a memory module. The data transfer in a first direction is at a first pulse amplitude modulation (PAM) level and in a second direction at a second PAM level. When receiving an indication of an increased demand for data transfer in the first direction, the memory controller increases the first PAM level to a target PAM level for data transfer in the first direction while maintaining the clock frequency and the second PAM level in the second direction.

Abstract: An integrated circuit includes a host die and a base die, both of which are disposed on an interposer. The host die includes multiple processors, and the base die includes at least two high-bandwidth memory (HBM) stacks that are disposed on the base die and communicate with the host die through the base die and the interposer. The at least two HBM stacks and the host die are arranged in a row with the host die at one end of the row. The base die further includes a controller circuit operative to multiplex outgoing data from the at least two HBM stacks to the host die, and demultiplex incoming data from the host die to the at least two HBM stacks.

Abstract: Heterogeneous integration semiconductor packages with voltage regulation are described. A semiconductor device can include a chip including a memory device and a plurality of through-silicon-vias (TSVs). The semiconductor device can further include a processor arranged on top of the chip. The processor can be configured to communicate with the memory device via a plurality of interconnects. The semiconductor device can further include at least one voltage regulator arranged on top of the chip. The at least one voltage regulator can be configured to regulate power being provided from the plurality of TSVs to the processor.

Abstract: Methods for forming three-dimensional dynamic random-access memory (3D DRAM) structures that leverage a grid pattern of high aspect ratio holes to form subsequent features of the 3D DRAM. The method may include depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) using an heteroepitaxy process onto a substrate and HAR etching of a pattern of holes into the substrate. The holes configured to provide chemistry access to laterally etch or deposit materials to form 3D DRAM features without requiring subsequent HAR etching of holes to form the 3D DRAM features.

Abstract: A system, method, and computer program product for a neural network inference engine is disclosed. The inference engine system may include a first memory and a processor in communication with the first memory. The processor may be configured to perform operations. The operations the processor is configured to perform may include fetching a first task with said first memory and delivering the first task to the processor for processing the first task. The operations may further include prefetching a second task with the first memory while the processor is processing the first task. The operations may further include the first memory delivering the second task to the processor upon completion of processing the first task. The operations may further include the processor processing the second task.

Abstract: A system may include a plurality of temperature sensors including an inlet temperature sensor for sensing an inlet temperature into the system of a cooling airflow and an outlet temperature sensor for sensing a measured exhaust temperature from the system of the cooling airflow and a thermal manager configured to execute an energy balance calculation to calculate a virtual outlet temperature based at least on the inlet temperature, determine if a temperature difference between the measured exhaust temperature and the virtual outlet temperature is more than a threshold difference, and take a remedial action if the temperature difference is more than the threshold difference.

Abstract: Systems and methods described provide a multiple-input multiple-output (MIMO) optimization service. A network device in a RAN predicts high usage thresholds and available per-service resources for supporting MIMO transmissions. The network device identifies, based on the predicted usage thresholds, user equipment (UE) devices that have a high-throughput session and have high usage levels on a cell. The network device assigns, based on the predicted available per-service resources, sounding reference signal (SRS)-based MIMO resources to the UE devices in the cell and assigns codebook-based MIMO resources to other UE devices in the cell.

Abstract: A film stack is formed a workpiece. The film stack is fabricated by sequentially depositing a carbon-doped silicon germanium stack and a silicon film to form a carbon-doped silicon-germanium and silicon mini-stack disposed on a substrate during a deposition cycle. The deposition cycle comprises exposing a workpiece including the substrate to a first gas including a first precursor to deposit a first silicon-germanium layer and exposing the workpiece to a second gas including the first precursor to deposit a carbon-silicon-germanium layer on the first silicon-germanium layer. Further, the deposition cycle includes exposing the workpiece to a third gas including the first precursor to deposit a second silicon-germanium layer on the carbon-silicon-germanium layer. The deposition cycle further includes exposing the workpiece to a fourth gas including a second precursor to deposit the silicon film on the second silicon-germanium layer. The second precursor differs from the first precursor.

Abstract: The present invention generally relates to the field of computational brain modeling. It is challenging to analyse neuronal activities that governs neuronal dynamics during the decision-making process using conventional techniques. Thus, embodiments of present disclosure provide a method and system to identify neuronal ensembles in basal ganglia using hierarchical drift-diffusion modeling. Microelectrode recording data of neuronal activity of neurons in the nuclei within BG of a subject are obtained. Then, spikes and associated spike times are extracted from the obtained data using which Inter-Spike Intervals (ISIs) for each of the neurons are calculated. Response times of each neuron is determined based on the ISIs and they are classified as one of an active state and a resting state which inherently reflected the broader network states responsible for behavioral responses by the neurons. Finally, the neurons are grouped into neuronal ensembles based on HDDM latent variables like drift rate.

Abstract: An electronic structure is provided in which the thermal conductance in a semiconductor die including backside back-end-of-the-line (BS-BEOL) structure located on a backside of a front-end-of-the-line (FEOL) level including one or more semiconductor devices, and a frontside back-end-of-the-line (FS-BEOL) structure located on a frontside of the FEOL level is improved by positioning power wires present in the backside BEOL structure in closer proximity to a thermal dissipation structure than signal wires present in the frontside BEOL structure.

Abstract: The disclosure includes receiving one or more updates to a global resource pool of a hybrid cloud and updating a local resource pool with the one or more updates to the global resource pool; intercepting a service request from an application; redirecting deployment of the service request to a resource provider of the hybrid cloud with available computing resources to fulfill the service request based at least in part on the local resource pool and by using a webhook; receiving an Internet Protocol (IP) address of the resource provider; redirecting a domain name service (DNS) of the application to the IP address of the resource provider; and sending the service request to the resource provider.