Patents by Inventor Arvind Kumar

Arvind Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12189550
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: January 7, 2025
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20250005371
    Abstract: A method for training and fine-tuning an artificial intelligence model is disclosed. In one embodiment, such a method distributes, across multiple chiplets of a package, functionality associated with a deep neural network. The method implements, within a first set of chiplets, frozen layers of the deep neural network. By contrast, the method implements, within a second set of chiplets, trainable layers of the deep neural network. The number of chiplets in the second set may be smaller than the number of chiplets in the first set and may consist of a single chiplet in some embodiments. In certain embodiments, the second set of chiplets has one or more of additional memory capacity and additional processing capacity compared to the first set of chiplets in order to train and fine tune the trainable layers. A corresponding apparatus is also disclosed.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: International Business Machines Corporation
    Inventors: Arvind Kumar, Mudhakar Srivatsa, Raghu Kiran Ganti, Joshua M. Rubin
  • Publication number: 20240429048
    Abstract: A semiconductor device and a method for manufacturing thereof. A substrate is provided. At least one silicon layer is formed on top of the substrate. At least one silicon-germanium layer is formed on top of at least one silicon layer. At least one silicon-germanium layer includes at least one n-type dopant. The semiconductor device having at least one silicon layer and at least one silicon-germanium layer is formed.
    Type: Application
    Filed: June 17, 2024
    Publication date: December 26, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Ruiying HAO, Thomas KIRSCHENHEITER, Arvind KUMAR, Mahendra PAKALA, Roya BAGHI, Balasubramanian PRANATHARTHIHARAN, Fredrick FISHBURN
  • Publication number: 20240422204
    Abstract: An method for load balancing session initiation protocol (SIP) registration requests using Cx health status includes monitoring, by an S-CSCF, at least one health parameter of a Cx interface associated with the S-CSCF. The method further includes determining, by the S-CSCF, a health category of the Cx interface associated with the S-CSCF based on the at least one health parameter. The method further includes sending, by the S-CSCF to an Interrogating Call Session Control Function (I-CSCF), an indication of the health category of the Cx interface associated with the S-CSCF. The method further includes load balancing, by the I-CSCF, SIP registration requests between the S-CSCF and at least one additional S-CSCF based on the received indication of the health category of the Cx interface associated with the S-CSCF.
    Type: Application
    Filed: June 13, 2023
    Publication date: December 19, 2024
    Inventors: Arvind Kumar Singh, Agnivesh Kumpati
  • Publication number: 20240416305
    Abstract: A continuous method for making granules of methylene urea-isobutylene diurea (MU-IBDU) includes: injecting an MU-IBDU slurry including water and MU-IBDU particles into a fluid bed granulator, wherein the fluid bed granulator includes seed particles: injecting air into the fluid bed granulator to fluidize the seed particles in an air stream: spraying the MU-IBDU slurry over the fluidized seed particles to form granules of MU-IBDU; and removing the granules of MU-IBDU from the fluid bed granulator. Fertilizer compositions including the MU-IBDU granules are also described.
    Type: Application
    Filed: October 18, 2022
    Publication date: December 19, 2024
    Inventors: Radha ACHANATH, Arvind KUMAR, Kavya AT
  • Publication number: 20240421587
    Abstract: A wireless power transfer system is disclosed. The wireless power transfer system includes a first converting unit configured to convert a first DC voltage of an input power to an AC voltage. Further, the wireless power transfer system includes a contactless power transfer unit configured to transmit the input power having the AC voltage. Also, the wireless power transfer system includes a second converting unit configured to convert the AC voltage to a second DC voltage and transmit the input power having the second DC voltage to an electric load. Additionally, the wireless power transfer system includes a switching unit configured to decouple the electric load from the contactless power transfer unit if the second DC voltage across the electric load is greater than a first threshold value.
    Type: Application
    Filed: August 30, 2024
    Publication date: December 19, 2024
    Inventors: Kapil Jha, Arvind Kumar Tiwari, Yash Veer Singh, Olive Ray
  • Patent number: 12166449
    Abstract: The system and method described herein provide grid-forming control of a power generating asset having a double-fed generator connected to a power grid. Accordingly, a stator-frequency error is determined for the generator. The components of the stator frequency error are identified as a torsional component corresponding to a drivetrain torsional vibration frequency and a stator component. Based on the stator component, a power output requirement for the generator is determined. This power output requirement is combined with the damping power command to develop a consolidated power requirement for the generator. Based on the consolidated power requirement, at least one control command for the generator is determined and an operating state of the generator is altered.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: December 10, 2024
    Assignee: General Electric Renovables Espana, S.L.
    Inventors: Shan Shine, Jishnu Kavil Kambrath, Kapil Jha, Veena Padmarao, Arvind Kumar Tiwari, Subbarao Tatikonda
  • Patent number: 12167612
    Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: December 10, 2024
    Assignee: International Business Machines Corporation
    Inventors: Arvind Kumar, Joshua M. Rubin
  • Publication number: 20240390433
    Abstract: The present invention relates to genetically modified Bacillus subtilis, compositions, and uses thereof in production of biomolecules and heterologous proteins and for delivery of biomolecules and heterologous proteins in animals and associated methods for improving animal health.
    Type: Application
    Filed: September 21, 2022
    Publication date: November 28, 2024
    Inventors: Dharanesh Mahimapura Gangaiah, Arvind Kumar, Shrinivasrao Peerajirao Mane
  • Publication number: 20240390431
    Abstract: The present invention provides a method of inhibiting a viral respiratory disease, comprising: administering to a subject, in need thereof, an effective amount of L. reuteri strain 3632 and/or strain 3630, wherein L. reuteri strain 3632 and/or strain 3630 secrete mersacidin.
    Type: Application
    Filed: September 22, 2022
    Publication date: November 28, 2024
    Applicant: BiomEdit, LLC
    Inventors: Arvind Kumar, Dharanesh Mahimapura Gangaiah
  • Publication number: 20240388091
    Abstract: A method for controlling an active harmonic filter of an inverter-based resource includes receiving, via a maximum compensation tracker module, a grid feedback signal, determining, via the maximum compensation tracker module, a phase shift signal based, at least in part, on the grid feedback signal, applying, via the maximum compensation tracker module, a phase shift offset signal to the phase shift signal to obtain a modified phase shift signal, determining, via the maximum compensation tracker module, a voltage reference signal for the active harmonic filter based, at least in part, on the grid feedback signal and the modified phase shift signal; and controlling, via the maximum compensation tracker module, the active harmonic filter using the voltage reference signal, wherein the phase shift offset signal ensures that the active harmonic filter injects a current substantially out of phase of a targeted harmonic.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 21, 2024
    Inventors: Pushkar Chandrakant Chaudhari, Kapil Jha, Robert Gregory Wagoner, Werner Gerhard Barton, Saurabh Shukla, Arvind Kumar Tiwari
  • Patent number: 12149196
    Abstract: Systems and methods are disclosed for improved fault diagnostics of electrical machines under dynamic load oscillations. The systems and methods may rely on one or more different algorithms for performing such fault diagnostics. One example, algorithm may involve determining a ratio of an instantaneous real power and a reactive power of the motor.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: November 19, 2024
    Assignee: GE Infrastructure Technology LLC
    Inventors: Ali Shahid, Sumitha Mohan, Rupam Mukherjee, Arvind Kumar Tiwari, Balakrishna Pamulaparthy
  • Patent number: 12149065
    Abstract: A wireless power transfer system is disclosed. The wireless power transfer system includes a first converting unit configured to convert a first DC voltage of an input power to an AC voltage. Further, the wireless power transfer system includes a contactless power transfer unit configured to transmit the input power having the AC voltage. Also, the wireless power transfer system includes a second converting unit configured to convert the AC voltage to a second DC voltage and transmit the input power having the second DC voltage to an electric load. Additionally, the wireless power transfer system includes a switching unit configured to decouple the electric load from the contactless power transfer unit if the second DC voltage across the electric load is greater than a first threshold value.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 19, 2024
    Assignee: General Intellectual Property Licensing, LLC
    Inventors: Kapil Jha, Arvind Kumar Tiwari, Yash Veer Singh, Olive Ray
  • Publication number: 20240365916
    Abstract: A high ankle combat boot has multilayered constructions in upper and sole and has a protective function against toxic chemical agents, especially chemical warfare agents. An outer layer in the multilayered upper, away from the foot when the boot is worn, and an inner layer, faces towards the boot. An adsorption layer based on adsorbent material, especially activated carbon spheres, which absorbs toxic chemical agents, especially chemical warfare agents is arranged between the outer layer and the inner layer of the upper. An outsole in the multilayered sole, away from the foot, and an insock, faces towards the foot. An insole based on multilayered aramid cloth, which resists the puncture through the sole when stepping over sharp objects, to prevent infiltration of toxic chemical agents, especially chemical warfare agents, is arranged between the insock and outsole. Efficient protection and a high degree of comfort are achieved.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 7, 2024
    Inventors: Prabhat Garg, Vikas Baburao Thakare, Imran Mohammad, Atul Kumar Sonkar, Virendra Vikram Singh, Pushpendra Kumar Sharma, Arvind Kumar Gupta
  • Publication number: 20240358989
    Abstract: Fluid connector systems including first and second connector portions couplable together to form a fluid pathway therethrough and can selectively resist or permit separation as desired. A connector portion can include a connector housing and a cover portion. The connector housing includes a connector body and an engagement portion. The connector body defines a housing volume, a luer opening and a mating opening. The housing volume is in fluid communication with the luer opening and the mating opening. The engagement portion may include an engagement lip extending radially toward the connector body. The engagement lip is configured to releasably engage the connector housing with a mating connector portion. The cover portion is configured to selectively surround the engagement portion of the connector housing. The cover portion is slidable to engage with the engagement portion of the connector housing and prevent release of the connector housing with the mating connector portion.
    Type: Application
    Filed: April 25, 2023
    Publication date: October 31, 2024
    Inventors: Leah Paige Gaffney, Abin Austin, Aman Desai, Mohammed Mehtab Khan, Amarsinh Deeliprao Jadhav, Narsi Reddy Sanikommu, Anuj Niranjanchavan, Sachin Gawali, Prashant Dalavi, Arvind Kumar Mishra, Vinay Kumar Kushwaha, Akshay Vidap, Richard Edward Byrd, Nakul Sudarshan
  • Publication number: 20240360278
    Abstract: The invention relates to a process for preparing a polyether polyol comprising: continuously feeding into a reactor which contains a composite metal cyanide complex catalyst and (i) a poly(oxyalkylene) polyol or (ii) a polyether polyol obtainable by the process according to the invention: (a) ethylene oxide, (b) a substituted alkylene oxide corresponding to Formula (I) in which R1, R2, R3 and R4 independently of each other represent hydrogen, a C1-C12-alkyl group and/or a phenyl group, provided that: (I) at least one of the radicals R1 to R4 does not represent hydrogen and (II) one or more methylene groups in any C1-C12-alkyl radical may be replaced by an oxygen atom or a sulfur atom, (c) optionally a starter compound having a hydroxyl functionality of from 1 to 8, wherein the weight ratio of the total amount of ethylene oxide fed to the total amount of the substituted alkylene oxide fed is of from 50:50 to 95:5, and wherein the ethylene oxide concentration is below 13,000 parts per million by weight (ppm
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Prashant Anil TATAKE, Prem Kumar DHANAPAL, Michiel Barend ELEVELD, Rama Tejaswi KARIPEDDI, Arvind KUMAR
  • Publication number: 20240355929
    Abstract: A memory device including at least one transistor having a dual gate structure comprising a first gate metal and a second gate metal, wherein the first gate metal has a work function of less than 4.55 eV and the second gate metal has a work function greater than 4.55 eV. A method of forming the memory device is also provided.
    Type: Application
    Filed: April 12, 2024
    Publication date: October 24, 2024
    Inventors: Arvind Kumar, Mahendra Pakala, Sanjeev Manhas, Imtiyaz Ahmad Khan
  • Patent number: 12119335
    Abstract: Embodiments of one or more high bandwidth chips (HB chips), e.g., high bandwidth memories (HBMs), are mounted on a module substrate. The HB chips/HBMs each have one or more HBM parallel communication interfaces (HB chip PHYs or HBM PHYs, respectively) that are connected to a companion PHY through a compatible companion PHY parallel connection that enable communication between the HBM PHY and the companion PHY. A companion PHY parallel link connection connects to a SERDES parallel connection of a SERDES. The SERDES converts parallel data/information at the SERDES parallel connection to serial data/information at a SERDES serial connection, and visa-versa, that enables efficient high bandwidth data transfer over longer distances. Alternative embodiments are disclosed.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: October 15, 2024
    Assignee: International Business Machines Corporation
    Inventors: Joshua M Rubin, Steven Lorenz Wright, Arvind Kumar, Mounir Meghelli
  • Publication number: 20240329793
    Abstract: Technologies for device management in metaverse interactions are disclosed. In an illustrative embodiment, a compute device is connected to remote compute devices in a metaverse. The compute device may detect local devices, such as by seeing a device in images captured by a camera of the compute device. The local device may be, e.g., a cell phone or smartwatch. The local devices may be registered by the compute device and reproduced in the metaverse. The local user of the compute device may interface with the local devices in the metaverse. The local user may allow remote users to interface or control the local device as well.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Aleksander Magi, Glen J. Anderson, Arvind Kumar, Meng Shi
  • Patent number: 12094525
    Abstract: A memory system, a method of assembling the memory system, and a computer system. The memory system includes a global memory device coupled to a plurality of processing elements. The global memory device is positioned external to a chip on which the plurality of processing devices reside. The memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. The memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. The one or more auxiliary scratchpads are configured to store static tensors. At least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: September 17, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ravi Nair, Swagath Venkataramani, Vijayalakshmi Srinivasan, Arvind Kumar