Patents by Inventor Asao Nishimura
Asao Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5895965Abstract: In order to provide a semiconductor device of high reliability which suppresses a degradation of the fatigue strength of solder connection portions and warping of a tape-type wiring substrate forming the cause of the inferior contact between solder bumps and an external substrate, and a method of manufacturing the semiconductor device, a frame-like member is disposed on the inner peripheral part of the tape-type wiring substrate so as to relax constraint on the thermal deformation of the tape-type semiconductor substrate.Type: GrantFiled: September 18, 1997Date of Patent: April 20, 1999Assignee: Hitachi, Ltd.Inventors: Naotaka Tanaka, Makoto Kitano, Akihiro Yaguchi, Ichiro Anjoh, Hideki Tanaka, Asao Nishimura
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Patent number: 5863817Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: March 24, 1998Date of Patent: January 26, 1999Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
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Patent number: 5821606Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: January 29, 1997Date of Patent: October 13, 1998Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
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Patent number: 5793099Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: May 7, 1996Date of Patent: August 11, 1998Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
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Patent number: 5698790Abstract: A method for measuring an adhesion strength of a resin material which is capable of accurately and readily measuring a universal adhesion strength independent of dimensions and shapes of specimen. A delamination portion is partially formed between a resin and an adherend material. Loads in two different directions are applied to an adhering interface such that opposed shear stresses are generated. As a result, a true adhering strength can be obtained from an apparent delamination propagating strength in each case.Type: GrantFiled: May 7, 1996Date of Patent: December 16, 1997Assignee: Hitachi, Ltd.Inventors: Asao Nishimura, Naotaka Tanaka, Isao Hirose
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Patent number: 5670793Abstract: A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.Type: GrantFiled: September 14, 1995Date of Patent: September 23, 1997Assignee: Hitachi, Ltd.Inventors: Hideo Miura, Shunji Moribe, Hisayuki Kato, Atsuyoshi Koike, Shuji Ikeda, Asao Nishimura
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Patent number: 5643805Abstract: A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.Type: GrantFiled: March 10, 1995Date of Patent: July 1, 1997Assignee: Hitachi, Ltd.Inventors: Hiroyuki Ohta, Hideo Miura, Hiroo Masuda, Yoichi Tamaki, Takahide Ikeda, Asao Nishimura, Takashi Hashimoto
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Patent number: 5635756Abstract: A semiconductor device of a structure in which lateral surfaces of a semiconductor element and an element supporting member are bonded to each other without resorting to use of a base member on which the semiconductor element is disposed. Since thicknesses of the base member and a bonding resin provides no contribution to overall thickness of the semiconductor device, reduction of thickness thereof by 30 to 40% is made possible. In dependent on configuration of the element supporting member, the semiconductor device can be applied to large size elements, lead-on-chip structure (LOC) and others.Type: GrantFiled: January 6, 1995Date of Patent: June 3, 1997Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura
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Patent number: 5619069Abstract: A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.Type: GrantFiled: June 2, 1995Date of Patent: April 8, 1997Assignee: Hitachi, Ltd.Inventors: Hiroyuki Ohta, Hideo Miura, Hiroo Masuda, Yoichi Tamaki, Takahide Ikeda, Asao Nishimura, Takashi Hashimoto
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Patent number: 5612569Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: June 5, 1995Date of Patent: March 18, 1997Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
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Patent number: 5608265Abstract: A semiconductor device, provided in a plastic encapsulated package, having a semiconductor chip, a lead and a member for electrically connecting them together. The semiconductor device has one or more first holes respectively extending from one surface of the package to a first side of the lead which is provided inside of the package, and has one or more second holes formed which are aligned with the first holes, respectively, in a manner such that each second hole is extended from the opposing surface of the package to a corresponding location on a second side of the lead and is aligned with a corresponding, opposing first hole, in the package, extending to the first side of the lead. These holes are provided as a plurality of sets of individual pairs of aligned holes respectively extending inwardly, from opposing surfaces of the package, to opposite sides of the corresponding leads.Type: GrantFiled: March 9, 1994Date of Patent: March 4, 1997Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Naotaka Tanaka, Tetsuo Kumazawa
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Patent number: 5571428Abstract: A method of producing a leadframe for use in semiconductor devices, comprises the steps of forming a space between leads 1a and 1b which are to be overlapped and welded each other, and welding the leads at a region including the space and melting and cutting off one of the leads. In one of the leads which is melted, cohesion and separation of molten metal occur in the region around the space. As a result, unnecessary portions such as an outer frame used for positioning can be cut off at the same time when the leads are connected by welding. Thus, high precision positioning of a plurality of element leadframes as well as high assembling productivity are achieved.Type: GrantFiled: April 18, 1995Date of Patent: November 5, 1996Assignee: Hitachi, Ltd.Inventors: Asao Nishimura, Akihiro Yaguchi, Mitsuaki Haneda, Ichiro Anjoh, Junichi Arita, Akihiko Iwaya, Masahiro Ichitani
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Patent number: 5537884Abstract: A method for measuring an adhesion strength of a resin material which is capable of accurately and readily measuring a universal adhesion strength independent of dimensions and shapes of specimen. A delamination portion is partially formed between a resin and an adherend material. Loads in two different directions are applied to an adhering interface such that opposed shear stresses are generated. As a result, a true adhering strength can be obtained from an apparent delamination propagating strength in each case.Type: GrantFiled: August 8, 1994Date of Patent: July 23, 1996Assignee: Hitachi, Ltd.Inventors: Asao Nishimura, Naotaka Tanaka, Isao Hirose
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Patent number: 5539250Abstract: A plastic-molded-type semiconductor device is provided wherein two semiconductor chips, having main surfaces on which electrodes and circuits are formed, are arranged to face each other. A lead frame is placed between these two semiconductor chips and electrically connected to their electrodes, and a plastic package is formed by plastic-sealing the above components. To provide for secure and convenient electrical connections between the electrodes on the semiconductor chips and the lead frame, wiring patterns are provided on the main surfaces of the semiconductor chips through the intermediation of insulating films. With this structure, it is possible for two large-sized semiconductor chips having electrodes in their middle sections to be encased in a single, relatively thin package.Type: GrantFiled: June 11, 1991Date of Patent: July 23, 1996Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Ryuji Kohno, Nae Yoneda
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Patent number: 5530286Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: August 22, 1994Date of Patent: June 25, 1996Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
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Patent number: 5488254Abstract: A plastic-molded-type semiconductor device is designed to prevent interfaces of a heat conductive member for heat radiation and plastic encapsulant from being separated from each other. The device is of a structure in which the heat conductive member for heat radiation is provided on and thermally connected to one side of a semiconductor chip, and the whole chip and the whole or a part of side surfaces of the heat conductive member are covered with the resin, the opposite side of the heat conductive member being exposed. In this structure, that portion of the heat conductive member which is covered with the resin has a cross-section whose configuration is any one of a circle, an ellipse, a polygon with corner portions whose internal angle is less than 180 degrees and a dull angle or which are rounded to have a low curvature.Type: GrantFiled: March 29, 1994Date of Patent: January 30, 1996Assignee: Hitachi, Ltd.Inventors: Asao Nishimura, Makoto Kitano, Ichio Shimizu
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Patent number: 5437915Abstract: A method of producing a leadframe for use in semiconductor devices, comprises the steps of forming a space between leads 1a and 1b which are to be overlapped and welded each other, and welding the leads at a region including the space and melting and cutting off one of the leads. In one of the leads which is melted, cohesion and separation of molten metal occur in the region around the space. As a result, unnecessary portions such as an outer frame used for positioning can be cut off at the same time when the leads are connected by welding. Thus, high precision positioning of a plurality of element leadframes as well as high assembling productivity are achieved.Type: GrantFiled: June 16, 1994Date of Patent: August 1, 1995Assignee: Hitachi, Ltd.Inventors: Asao Nishimura, Akihiro Yaguchi, Mitsuaki Haneda, Ichiro Anjoh, Junichi Arita, Akihiko Iwaya, Masahiro Ichitani
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Patent number: 5391916Abstract: A semiconductor device of a structure in which lateral surfaces of a semiconductor element and an element supporting member are bonded to each other without resorting to use of a base member on which the semiconductor element is disposed. Since thicknesses of the base member and a bonding resin provides no contribution to overall thickness of the semiconductor device, reduction of thickness thereof by 30 to 40% is made possible. In dependence on configuration of the element supporting member, the semiconductor device can be applied to large size elements, lead-on-chip structure (LOC) and others.Type: GrantFiled: June 14, 1993Date of Patent: February 21, 1995Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura
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Patent number: 5359899Abstract: A method for measuring an adhesion strength of a resin material which is capable of accurately and readily measuring a universal adhesion strength independent of dimensions and shapes of specimen. A delamination portion is partially formed between a resin and an adherend material. Loads in two different directions are applied to an adhering interface such that opposed shear stresses are generated. As a result, a true adhering strength can be obtained from an apparent delamination propagating strength in each case.Type: GrantFiled: May 18, 1993Date of Patent: November 1, 1994Assignee: Hitachi Ltd.Inventors: Asao Nishimura, Naotaka Tanaka, Isao Hirose
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Patent number: 5358904Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: December 14, 1992Date of Patent: October 25, 1994Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto