Patents by Inventor Asao Nishimura
Asao Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5357139Abstract: In a package for DRAM, plastic is included between the common signal inner leads (bus bar inner leads) and insulating films arranged in the central part of a semiconductor chip. Thus, the deformation of plastic at the upper edge of the common signal inner leads is reduced and no great stress is generated at this portion. Accordingly, plastic cracking can be prevented.Type: GrantFiled: September 8, 1993Date of Patent: October 18, 1994Assignee: Hitachi, Ltd.Inventors: Akihiro Yaguchi, Asao Nishimura, Makoto Kitano, Ryuji Kohno, Nae Yoneda, Ichiro Anjoh, Gen Murakami
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Patent number: 5347429Abstract: A plastic-molded-type semiconductor device includes a plurality of semiconductor chips, metallic wires connected to the semiconductor chips, leads connected to the metallic wires, and an insulating member interposed between the semiconductor chips and sealed in a resin member. Circuit formed surfaces of the semiconductor chips are directed in the same direction, and one or more of the semiconductor chips serve as a base on which the other semiconductor chips are mounted through the insulating member. One ends of the leads are bonded to the insulating member, and electrodes pad of each semiconductor chip are not covered by the other semiconductor chips, the insulating member and the leads, and therefore are exposed to the surface of the insulating member. In this device, the provision of a tab is omitted, and the laminated chips can be contained in a package thinner than a conventional package.Type: GrantFiled: May 28, 1993Date of Patent: September 13, 1994Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Nae Yoneda
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Patent number: 5299092Abstract: A plastic sealed type semiconductor apparatus includes at least two semiconductor devices which are disposed with a space therebetween in such a manner that circuit forming surfaces oppose each other, and an electric signal lead which is adhered to each of the circuit forming surfaces with an insulating member provided therebetween for electric insulation and which is electrically connected to the semiconductor device by a thin metal wire. The semiconductor devices and the electric signal leads are sealed with a resin in a state where the electric signal leads are laid on top of one another to form a plastic package. The overlaid portion of the electric signal leads has a surface contact portion of the leads and a resin providing portion. The resin providing portion is a recessed portion which is formed when the resin is molded in such a manner that it passes through the surface contact portion of the leads in the lateral direction thereof.Type: GrantFiled: May 22, 1992Date of Patent: March 29, 1994Assignee: Hitachi, Ltd.Inventors: Akihiro Yaguchi, Asao Nishimura, Makoto Kitano, Ichiro Anjoh, Junichi Arita
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Patent number: 5296737Abstract: A semiconductor device comprises a plurality of semiconductor chips; electrodes formed on circuit surfaces of said plurality of semiconductor chips; inner leads made of a metal foil and bonded at first ends thereof to the electrodes, outer leads each having a predetermined surface at a first end thereof bonded to a second end of at least one of the inner leads, and a sealing material sealing said plurality of semiconductor chips, the electrodes, the inner leads, and part of each of the outer leads. The semiconductor chips are laminated in such a manner that those surfaces of the semiconductor chips on which their respective circuits are formed are disposed in facing relation to each other. This provides a semiconductor device which is excellent in assembling efficiency.Type: GrantFiled: September 6, 1991Date of Patent: March 22, 1994Assignee: Hitachi, Ltd.Inventors: Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Gen Murakami, Ichiro Anjoh
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Patent number: 5295045Abstract: A plastic-molded-type semiconductor device having a high degree of integration encases a plurality of semiconductor chips in a package unit with each chip situated perpendicular to the substrate for mounting. On a surface of each chip containing circuits or on a reverse surface of the same, a lead frame is attached with an insulating material interposed therebetween. The chip and lead frame are connected with each other by using wire. The lead frame is arranged perpendicularly to another lead frame provided in parallel and connected therewith by welding. A printed circuit board may be used in place of said latter lead frame. By arranging the chips in projections made of resin, the thermal resistance of the semiconductor device is decreased. The present invention is particularly effective for a memory IC.Type: GrantFiled: November 14, 1991Date of Patent: March 15, 1994Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Nae Yoneda, Maya Obata, Ryuji Kohno, Mitsuaki Haneda
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Patent number: 5293068Abstract: An encapsulated semiconductor device has a chip, a chip pad having through holes and also conducting patterns corresponding to an electrode pad of the chip, and leads. An arbitrary external terminal arrangement is obtained by combining a wire bonding operation between the conducting pattern and lead. Wire bonding is advantageously performed between the leads and electrode pads of the semiconductor chip arranged at arbitrary positions. The degree of freedom in designing areas of the chips and also a printed circuit board is improved so that a high packaging density is achieved and furthermore the printed circuit board is made compact.Type: GrantFiled: October 13, 1992Date of Patent: March 8, 1994Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Sueo Kawai
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Patent number: 5287284Abstract: A product specification complex analysis system is provided which inputs product specifications of an external form and materials, design parameters determined by analysis and evaluation in the specifications, the range of the change of the parameters and a plurality of items of estimates as external input data, calls out and executes an evaluation program corresponding to each item of the estimates and stored in advance, from a group of evaluation programs whenever the item of the estimates is renewed, in order to sequentially evaluate the product specifications for each item of the estimates, determines the fluctuation of analysis results with respect to the change of the design parameters within designated ranges of changes, evaluates trade-off between the analysis results by changing the design parameters from the analysis results corresponding to the items of the estimates so as to make maximal evaluation values in an evaluation formula as an estimate function with weights comprising each of these analysType: GrantFiled: November 14, 1991Date of Patent: February 15, 1994Assignee: Hitachi, Ltd.Inventors: Kazuhiro Sugino, Shingo Akasaka, Hiroko Imanishi, Junichi Saeki, Kunihiko Nishi, Asao Nishimura
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Patent number: 5256903Abstract: A plastic encapsulated semiconductor device containing one or more of insulating films. Uneven surfaces, such as recesses and roughened surfaces, are strategically provided on peripheral side (edge) surfaces of the insulating films. As a result, therefore, an interface separation does not easily occur between the side surfaces of the insulating films and the encapsulating resin. If such an interface separation should occur, it cannot develop easily. Thus, it is possible to obtain a plastic encapsulated semiconductor device of a high level of reliability even when the largest possible semiconductor element is mounted therein within limited outside dimensions.Type: GrantFiled: November 26, 1991Date of Patent: October 26, 1993Assignee: Hitachi Ltd.Inventors: Maya Obata, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Ryuji Kohno, Nae Yoneda, Ichiro Anjoh, Gen Murakami
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Patent number: 5194935Abstract: The plastic encapsulated semiconductor device according to the present invention has a semiconductor chip, leads, and members for electrically connecting these parts to each other. A part of leads, the semiconductor chip and the connecting members are encapsulated with a plastic to form a package. The plate type plastic fins formed on the surface of and integrally with the package are divided in two directions perpendicular to each other thereby forming, for example, rows and columns of fins or fin segments, on the package surface. Therefore, the semiconductor device according to the present invention can be molded easily by a transfer molding. It has a high reliability with respect to the prevention of cracks in the plastic, and a low thermal resistance, and is most suitably used to obtain a high-density package mounting structure.Type: GrantFiled: January 29, 1991Date of Patent: March 16, 1993Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Sueo Kawai, Gen Murakami, Ichio Shimizu
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Patent number: 5159434Abstract: An encapsulated semiconductor device has a chip, a chip pad having through holes and also conducting patterns corresponding to an electrode pad of the chip, and leads. An arbitrary external terminal arrangement is obtained by combining a wire bonding operation between the conduting pattern and lead. Wire bonding is advantageously performed between the leads and electrode pads of the semiconductor chip arranged at arbitrary positions. The degree of freedom in designing areas of the chips and also a printed circuit board is improved so that a high packaging density is achieved and furthermore the printed circuit board is made compact.Type: GrantFiled: February 1, 1991Date of Patent: October 27, 1992Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Sueo Kawai
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Patent number: 5110537Abstract: A method and apparatus for inspecting the change in a water quality in terms of the change in a corrosion rate by detecting the capacity change between opposed electrodes due to the corrosion of electrode surfaces. As a result, the water quality can be continuously monitored over a long time while leaving the electrodes in the water to be inspected. Thus, the method and apparatus are suited for controlling the water quality especially in an atomic reactor vessel.Type: GrantFiled: February 26, 1990Date of Patent: May 5, 1992Assignee: Hitachi, Ltd.Inventors: Hideo Miura, Asao Nishimura, Shinji Sakata, Tasuku Shimizu, Shigeo Hattori
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Patent number: 5101263Abstract: In a plastic encapsulated semiconductor device, a part of wire piece may break down due to thermal fatigue, which positioned adjacent to a bonding portion of the wire piece connected to a chip. This is caused by that wire piece moves relative to plastic encapsulating the chip and the wire piece, and a strain in the wire piece due to thermal deformation of the device concentrates on one portion of the wire piece. Accordingly, a rugged portion is formed on a surface of a part of wire piece subjected to a breakdown to thermal fatigue. The plastic bites recesses of the rugged portion to prevent the wire piece from moving relative to the plastic, thereby preventing the wire piece from breaking down due to thermal fatigue.Type: GrantFiled: June 21, 1990Date of Patent: March 31, 1992Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Chikako Kitabayashi, Asao Nishimura, Hideo Miura, Akihiro Yaguchi, Sueo Kawai
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Patent number: 5068712Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: September 19, 1989Date of Patent: November 26, 1991Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
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Patent number: 5047837Abstract: A packaged semiconductor device having heat transfer leads carrying a semiconductor chip directly or indirectly through a chip pad and extended to the exterior of the plastic or ceramics seal of the package, and a heat transfer cap held in surface contact with the extended heat transfer leads and covering upper side of the package. The heat generated in the semiconductor chip is transmitted to the upper side of the package and to the printed circuit board only through metallic parts so that the heat transfer is enhanced to remarkably reduce thermal resistance, thus enabling packaging of a semiconductor chip having a large heat generation rate.Type: GrantFiled: August 3, 1989Date of Patent: September 10, 1991Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Takahiro Daikoku, Sueo Kawai, Ichio Shimizu, Kazuo Yamazaki, Asao Nishimura, Hideo Miura, Akihiro Yaguchi
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Patent number: 5041901Abstract: A lead frame having a plurality of inner leads and outer leads, said outer leads being subjected to surface treatment for improving solder wettability at an end portion and to sruface treatment for suppressing solder wettability at least at a portion neighboring to the end portion, or said outer leads being bent 4 times or more, is effective for improving thermal fatigue life and reliability when applied to a semi-conductor device.Type: GrantFiled: May 2, 1990Date of Patent: August 20, 1991Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Sueo Kawai, Akio Hoshi, Ichio Shimizu
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Patent number: 4987474Abstract: In a tabless lead frame wherein a space for laying inner leads is sufficiently secured when a lengthened and enlarged semiconductor pellet is placed or set in a resin-molding package, through holes are provided in leads for the purpose of increasing the occupation area ratio of a resin portion. Furthermore, each of the leads corresponding to the lower surface of the pellet is branched into a plurality of portions in the widthwise direction thereof in order to reduce a stress. Further, in an insulating sheet which is interposed between the leads and the pellet, the dimension of the shorter lateral sides thereof is set smaller than that of the shorter lateral sides of the pellet in order to prevent cracks from occurring at the end part of the insulating sheet.Type: GrantFiled: June 12, 1990Date of Patent: January 22, 1991Assignee: Hitachi, Ltd.Inventors: Toshihiro Yasuhara, Masachika Masuda, Asao Nishimura, Naozumi Hatada, Sueo Kawai, Makoto Kitano, Hideo Miura, Akihiro Yaguchi, Gen Murakami
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Patent number: 4942452Abstract: A lead frame and a semiconductor device wherein a through hole is formed in the center of a semiconductor chip-mounting surface of a chip pad at the center of the lead frame, the through hole being tapered or being one which corresponds to a surface area that is greater on the surface of the chip-mounting surface of the chip pad than on the surface of the side opposite to the chip-mounting surface thereof. This prevents the occurrence of cracks in the sealing plastic portion in the step of reflow soldering of the lead frame to the substrate.Type: GrantFiled: February 22, 1988Date of Patent: July 17, 1990Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Sueo Kawai, Asao Nishimura, Hideo Miura, Akihiro Yaguchi, Chikako Kitabayashi, Ichio Shimizu, Toshio Hatsuda, Toshinori Ozaki, Toshio Hattori, Souji Sakata
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Patent number: 4739381Abstract: A piezoresistive strain sensing device is comprised of a semiconductor single-crystal substrate, having crystal indices in the (100) phase, and having p-type and n-type diffused resistors formed therein. A diffused resistance gauge is formed of the p-type and n-type resistors. Temperature compensation means are formed adjacent the resistance gauge in the substrate.Type: GrantFiled: March 12, 1986Date of Patent: April 19, 1988Assignee: Hitachi, Ltd.Inventors: Hideo Miura, Tatsuji Sakamoto, Asao Nishimura