Abstract: MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

Abstract: Techniques are provided for fabricating semiconductor integrated circuit devices with embedded magnetic random-access memory (MRAM) devices. For example, a MRAM device and a multi-level bottom electrode via contact are formed within a back-end-of line layer. The MRAM device includes a memory device pillar having a bottom electrode, a magnetic tunnel junction structure, and an upper electrode. The multi-level bottom electrode via contact is disposed below and in contact with the bottom electrode. The multi-level bottom electrode via contact includes a first via contact disposed in a first insulation layer, and a second via contact disposed in a second insulation layer. The first and second insulation layers allow for sacrificial etching of the first and second insulation layers during formation of the MRAM device while retaining a sufficient thickness of remaining insulation material to serve as a capping layer to protect metallic wiring that is disposed in an underlying metallization layer.

Abstract: A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.

Abstract: A method for manufacturing a semiconductor device includes forming one or more memory device layers over a contact structure. In the method, a plurality of hardmask layers are deposited on the one or more memory device layers in a stacked configuration. Alternating hardmask layers of the stacked configuration are different from each other in at least one respect. The method further includes patterning the plurality of hardmask layers and the one or more memory device layers into a pillar over the contact structure.

Abstract: A semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes an embedded memory device and an electrode in contact with a top surface of the memory embedded device. A metal encapsulation layer is in contact with a top surface of the electrode and a portion of sidewalls of the electrode. The metal encapsulation layer comprises one or more materials that are chemical etch resistant and are conductive when oxidized. The method includes forming an insulating layer over a memory device and an electrode in contact with the memory device. Portions of the insulating layer are etched. The etching exposes a top surface and a portion of sidewalls of the electrode. A metal encapsulation layer is formed over and in contact with the top surface and the portion of sidewalls of the electrode.

Abstract: Techniques for EUV resist pattern transfer using a graded hardmask are provided. In one aspect, a method of patterning is provided. The method includes: forming a graded hardmask on a device stack; depositing a resist onto the graded hardmask; patterning the resist to form a pattern in the resist having at least one feature; modifying at least one surface region to increase an etch rate of the graded hardmask; transferring the pattern from the resist to the graded hardmask; and transferring the pattern from the graded hardmask to at least one underlying layer of the device stack. A device structure formed by the patterning method is also provided.

Abstract: A method of making a semiconductor device includes depositing an oxide material on a patterned mask arranged on a substrate. The method further includes removing a portion of the oxide material such that the patterned mask is exposed. The method also includes removing the patterned mask such that the substrate is exposed between areas of remaining oxide material.

Abstract: Techniques for forming barrierless contacts filled with Co are provided. In one aspect, a method for forming barrierless contacts includes: forming bottom metal contacts in a first ILD; depositing a second ILD on the bottom metal contacts; forming contact vias in the second ILD landing on the bottom metal contacts; selectively forming a liner on a top surface of the second ILD and on the second ILD along sidewalls of the contact vias; filling the contact vias with a metal; and removing an excess of the metal to form the barrierless contacts whereby metal-to-metal contact is present between the barrierless contacts and the bottom metal contacts. A contact structure is also provided.

Abstract: Techniques are provided for fabricating magnetic random-access memory devices, which eliminate junction shorts and minimize gouging of an underlying insulating layer. For example, a bottom electrode layer, a magnetic tunnel junction (MTJ) stack, and an upper electrode layer are formed over an insulating layer. The bottom electrode layer and the MTJ stack are etched to form an upper electrode and a MTJ structure. A cleaning etch process removes residual metallic material which is re-deposited on sidewalls of the MTJ structure as a result of etching the MTJ stack. A conformal dielectric layer is formed to encapsulate the upper electrode and the MTJ structure and prevent oxidation or re-deposition of metallic material on the cleaned sidewalls of the MTJ structure. A final etch process is performed to pattern the conformal dielectric layer and bottom electrode layer to form a spacer on sidewalls of the MTJ structure and form a bottom electrode.

Abstract: A method for manufacturing a semiconductor device includes forming one or more memory device layers over a contact structure. In the method, a plurality of hardmask layers are deposited on the one or more memory device layers in a stacked configuration. Alternating hardmask layers of the stacked configuration are different from each other in at least one respect. The method further includes patterning the plurality of hardmask layers and the one or more memory device layers into a pillar over the contact structure.

Abstract: A method for fabricating a semiconductor device includes forming misalignment tolerant vias each having a landing area configured to account for alignment mismatch resulting from subsequent formation of conductive structures, depositing a conductive layer over the misalignment tolerant vias, and obtaining conductive layer patterning including each of the conductive structures formed on at least a portion of a respective one of the landing areas, including subtractively patterning the conductive layer. The misalignment tolerant vias and the conductive structures imparting a semiconductor device geometry accounting for the alignment mismatch.

Abstract: A method for manufacturing a semiconductor device includes forming one or more memory device layers over a contact structure. In the method, a plurality of hardmask layers are deposited on the one or more memory device layers in a stacked configuration. Alternating hardmask layers of the stacked configuration are different from each other in at least one respect. The method further includes patterning the plurality of hardmask layers and the one or more memory device layers into a pillar over the contact structure.

Abstract: Embodiments of systems and methods for patterning features in tantalum nitride (TaN) are described. In an embodiment, a method may include receiving a substrate comprising a TaN layer. The method may also include etching the substrate to expose at least a portion of the TaN layer. Additionally, the method may include performing a passivation process to reduce lateral etching of the TaN layer. The method may further include etching the TaN layer to form a feature therein, wherein the passivation process is controlled to meet one or more target passivation objectives.

Abstract: A method for selectively encapsulating embedded memory pillars in a semiconductor device includes coating a passivation layer on a first dielectric surface on a first outer dielectric layer present in the semiconductor device. The passivation layer adheres to the dielectric surface selective to metal. The method includes depositing an encapsulation layer on side and top surfaces of the embedded memory pillars. The passivation layer prevents deposition of the encapsulation layer on the first dielectric surface of the first outer layer dielectric. The method includes removing the first outer dielectric layer from horizontal subraces around the embedded memory pillar and the encapsulation layer from the top surface of the embedded memory pillars.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack more particularly includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on the resist layer, the selective deposition of the metal-containing layer on the resist layer occurring after pattern development. The method further includes exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, and selectively depositing the metal-containing layer on the developed pattern in the resist layer. The selective deposition avoids deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer.

Abstract: A method for forming one or more self-aligned contacts on a semiconductor device includes applying a protective layer on an oxide surface above a source and drain of the semiconductor device. The protective layer covers a top surface of the oxide surface selective to nitride above a gate contact pillar. A sacrificial layer is applied to the nitride surface. The sacrificial layer is deposited only on the nitride surface that is selective to the oxide layer coated with the protective layer. The protective layer is removed from the oxide surface and source/drain contact holes are etched in the oxide surface to form self-aligned contacts on the semiconductor device.

Abstract: A method includes forming a first insulating layer having one or more vias formed in at least a portion of the first insulating layer. The vias are filled with a first metallic material. A cap layer is deposited on a top surface of the first insulating layer and a top surface of the one or more vias and a second insulating layer is deposited on a top surface of the cap layer. One or more openings are formed in the second insulating layer and the cap layer. A self-assembled monolayer is formed on an exposed top surface of the first metallic material in the one or more vias. A barrier layer is formed on at least the exposed surface of the one or more openings. The self-assembled monolayer is removed and the one or more openings are filled with a second metallic material.

Abstract: A method for manufacturing a semiconductor device includes forming one or more memory device layers over a contact structure. In the method, a plurality of hardmask layers are deposited on the one or more memory device layers in a stacked configuration. Alternating hardmask layers of the stacked configuration are different from each other in at least one respect. The method further includes patterning the plurality of hardmask layers and the one or more memory device layers into a pillar over the contact structure.

Abstract: A method for fabricating a semiconductor device includes forming a first encapsulation layer along the device, including forming the first encapsulation layer along a memory device region associated with a memory device, forming an intermediate layer on the first encapsulation layer to enable etch endpoint detection and endpoint-based process control for encapsulation layer etch back, and forming a second encapsulation layer on the intermediate layer.