Abstract: A method of manufacturing a semiconductor device includes forming a hard mask layer over a substrate and activating a surface of the hard mask layer to form a surface active layer over the hard mask layer. A resist layer is formed over the hard mask layer and a metal-containing layer is selectively formed over the surface active layer in at least one trench defined between portions of the resist layer. The resist layer is removed to define a pattern between portions of the selectively formed metal-containing layer and the hard mask layer is etched in accordance with the pattern. The etched pattern is transferred to at least a portion of the substrate and at least a portion of the hard mask layer, surface active layer, and metal-containing layer are removed.

Abstract: A method of manufacturing a semiconductor device includes forming a hard mask layer over a substrate and activating a surface of the hard mask layer to form a surface active layer over the hard mask layer. A resist layer is formed over the hard mask layer and a metal-containing layer is selectively formed over the surface active layer in at least one trench defined between portions of the resist layer. The resist layer is removed to define a pattern between portions of the selectively formed metal-containing layer and the hard mask layer is etched in accordance with the pattern. The etched pattern is transferred to at least a portion of the substrate and at least a portion of the hard mask layer, surface active layer, and metal-containing layer are removed.

Abstract: A semiconductor structure comprises a semiconductor substrate, and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack comprises at least a hard mask layer and a resist layer formed over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on a developed pattern of the resist layer through inclusion in the hard mask layer of one or more materials inhibiting deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer. The hard mask layer illustratively comprises, for example, at least one of a grafted self-assembled monolayer configured to inhibit deposition of the metal-containing layer, and a grafted polymer brush material configured to inhibit deposition of the metal-containing layer.

Abstract: Methods for post-lithographic inspection using an e-beam inspection tool of organic EUV sensitive photoresists generally includes conformal deposition of a silicon derivative or a metal oxide onto the relief image, wherein the silicon derivative is a material selected to have a dielectric constant that is greater than the dielectric constant of the underlying organic EUV sensitive photoresist. The conformal deposition of the silicon derivative or the metal oxide includes a low temperature vapor deposition process of less than about 100° C. to provide a coating thickness of less than about 5 nanometers.

Abstract: A method is presented for transferring patterns to underlying films in patterning stacks. The method includes forming a lithographic stack over a hard mask stack, forming a photoresist layer over the lithographic stack, depositing a conductive cap over the photoresist layer, depositing an organic gap filling material over the conductive cap, and recessing the organic gap filling material to expose top surfaces of the conductive cap. The method further includes etching the exposed top surfaces of the conductive cap to expose top surfaces of the photoresist layer, removing the photoresist layer such that conductive cap sections remain over the lithographic stack, and forming trenches into the lithographic stack and the hard mask stack by using the conductive cap sections as a mask.

Abstract: Methods for post-lithographic inspection using an e-beam inspection tool of organic EUV sensitive photoresists generally includes conformal deposition of a silicon derivative or a metal oxide onto the relief image, wherein the silicon derivative is a material selected to have a dielectric constant that is greater than the dielectric constant of the underlying organic EUV sensitive photoresist. The conformal deposition of the silicon derivative or the metal oxide includes a low temperature vapor deposition process of less than about 100° C. to provide a coating thickness of less than about 5 nanometers.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack more particularly includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on the resist layer, the selective deposition of the metal-containing layer on the resist layer occurring after pattern development. The method further includes exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, and selectively depositing the metal-containing layer on the developed pattern in the resist layer. The selective deposition avoids deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer.

Abstract: Embodiments of systems and methods for patterning features in tantalum nitride (TaN) are described. In an embodiment, a method may include receiving a substrate comprising a TaN layer. The method may also include etching the substrate to expose at least a portion of the TaN layer. Additionally, the method may include performing a passivation process to reduce lateral etching of the TaN layer. The method may further include etching the TaN layer to form a feature therein, wherein the passivation process is controlled to meet one or more target passivation objectives.

Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

Abstract: Various embodiments of the present invention are directed to a method for fabricating a memory cell comprising performing a passivation step on a cell structure and cell source lines prior to exhuming a masking layer to prevent oxidation of the cell structure and source lines.