Patents by Inventor Ashish A. Verma
Ashish A. Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230420510Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Inventors: Carl H. NAYLOR, Kirby MAXEY, Kevin P. O'BRIEN, Chelsey DOROW, Sudarat LEE, Ashish Verma PENUMATCHA, Uygar E. AVCI, Matthew V. METZ, Scott B. CLENDENNING, Jiun-Ruey CHEN, Chia-Ching LIN, Carly ROGAN
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Publication number: 20230411390Abstract: In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Applicant: Intel CorporationInventors: Kevin P. O'Brien, Ande Kitamura, Ashish Verma Penumatcha, Carl Hugo Naylor, Kirby Maxey, Rachel A. Steinhardt, Scott B. Clendenning, Sudarat Lee, Uygar E. Avci, Chelsey Dorow
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Patent number: 11816131Abstract: A method and system. Target clusterability is calculated as an average of a respective clusterability of at least one target data item comprised by a target domain. Target-side matchability is calculated as an average of a respective matchability of each target centroid of the target domain to source centroids of a source domain, wherein the source domain comprises at least one source data item. Source-side matchability is calculated as an average of a respective matchability of each source centroid of said source centroids to the target centroids. Source-target pair matchability is calculated as an average of the target-side matchability and the source-side matchability. Cross-domain clusterability between the target domain and the source domain is calculated as a linear combination of the calculated target clusterability and the calculated source-target pair matchability. The cross-domain clusterability is transferred to a device.Type: GrantFiled: March 25, 2019Date of Patent: November 14, 2023Assignee: KYNDRYL, INC.Inventors: Jeffrey M. Achtermann, Indrajit Bhattacharya, Kevin W. English, Shantanu R. Godbole, Sachindra Joshi, Ashwin Srinivasan, Ashish Verma
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Publication number: 20230352584Abstract: Technologies for a transistor with a ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a ferroelectric gate dielectric that is lattice matched to the channel of the transistor. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one transistor memory cell.Type: ApplicationFiled: May 2, 2022Publication date: November 2, 2023Inventors: Dmitri Evgenievich Nikonov, Chia-Ching Lin, Uygar E. Avci, Tanay A. Gosavi, Raseong Kim, Ian Alexander Young, Hai Li, Ashish Verma Penumatcha, Ramamoorthy Ramesh, Darrell G. Schlom
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Publication number: 20230349983Abstract: Technical solutions are described for diagnosing an input power supply providing power to a motor. A method includes: generating a sinusoidal stimulus signal; applying, using the input power supply, the sinusoidal stimulus signal to the motor; measuring a response to the sinusoidal stimulus signal; determining a degraded condition of the input power supply based on the response to the sinusoidal stimulus signal; and performing an action in response to determining the degraded condition of the input power supply.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Inventors: Nicholas E. Gizinski, Julie A. Kleinau, David M. Williams, Clayton D. Larson, Steven J. Collier-Hallman, Ashish Verma
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Publication number: 20230317783Abstract: Embodiments described herein may be related to forming nano ribbon transistors using layered 2D semiconductor channels. The layered 2D semiconductor channels may be created by forming a scaffold structure that has a first edge that extends from a silicon-based substrate, and a second edge opposite the first edge that is distal to the silicon based substrate. Alternating layers of 2D semiconductor material and a 3D semiconductor material may then be built on the second edge of the scaffold structure. In embodiments, the 3D semiconductor material may then be removed and a gate material deposited around at least a portion of the layers of 2D semiconductor material.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Kirby MAXEY, Carl H. NAYLOR, Uygar E. AVCI, Chelsey DOROW, Kevin P. O'BRIEN, Scott B. CLENDENNING, Matthew V. METZ, Chia-Ching LIN, Sudarat LEE, Ashish Verma PENUMATCHA
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Patent number: 11769789Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.Type: GrantFiled: March 28, 2019Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Nazila Haratipour, Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Owen Loh, Mengcheng Lu, Seung Hoon Sung, Ian A. Young, Uygar Avci, Jack T. Kavalieros
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Patent number: 11763082Abstract: Methods, systems, and computer program products for accelerating inference of transformer-based models are provided herein. A computer-implemented method includes obtaining a machine learning model comprising a plurality of transformer blocks, a task, and a natural language dataset; generating a compressed version of the machine learning model based on the task and the natural language dataset, wherein the generating comprises: obtaining at least one set of tokens, wherein each token in the set corresponds to one of the items in the natural language dataset, identifying and removing one or more redundant output activations of different ones of the plurality of transformer blocks for the at least one set of tokens, and adding one or more input activations corresponding to the one or more removed output activations into the machine learning model at subsequent ones of the plurality of the transformer blocks; and outputting the compressed version of the machine learning model to at least one user.Type: GrantFiled: July 12, 2021Date of Patent: September 19, 2023Assignee: International Business Machines CorporationInventors: Saurabh Goyal, Anamitra Roy Choudhury, Saurabh Manish Raje, Venkatesan T. Chakaravarthy, Yogish Sabharwal, Ashish Verma
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Publication number: 20230281518Abstract: Second machine learning models trained using respective second data sets can be received. The second machine learning models can be run using a first data set used in training a first machine learning model, where the second machine learning models produce respective outputs. Scores associated with the second machine learning models can be determined by comparing the respective outputs with ground truth associated with the first data set. Based on the scores associated with the second machine learning models, whether the first data set is to be discarded or kept can be determined for training the first machine learning model.Type: ApplicationFiled: March 4, 2022Publication date: September 7, 2023Inventors: Dinesh C. Verma, Supriyo Chakraborty, Shiqiang Wang, Augusto Vega, Hazar Yueksel, Ashish Verma, Pradip Bose, Jayaram Kallapalayam Radhakrishnan
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Patent number: 11742407Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack.Type: GrantFiled: December 2, 2019Date of Patent: August 29, 2023Assignee: Intel CorporationInventors: Seung Hoon Sung, Ashish Verma Penumatcha, Sou-Chi Chang, Devin Merrill, I-Cheng Tung, Nazila Haratipour, Jack T. Kavalieros, Ian A. Young, Matthew V. Metz, Uygar E. Avci, Chia-Ching Lin, Owen Loh, Shriram Shivaraman, Eric Charles Mattson
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Publication number: 20230253475Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.Type: ApplicationFiled: April 3, 2023Publication date: August 10, 2023Applicant: Intel CorporationInventors: Tanay Gosavi, Chia-Ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Publication number: 20230254662Abstract: A computer-implemented method enables registered mobile device users associated with a common matter to identify each other in a court-complex setting, and to communicate with each other directly using mobile devices once the registered mobile device users enter a code associated to the common matter. A server-side application receives and processes user and/or firm names to effect registration. Using the mobile device application, a first registered mobile device user enters a code associated with the common matter, received by the server-side application that receives and processes the code, effecting check in by the first registered mobile device user. Using the mobile application, a second registered user enters the code associated with the common matter, enabling the first and second registered mobile device user associated with the common matter to communicate over a wireless network using Voice over Internet Protocol (VoIP), Wi-Fi and/or cellular telephony.Type: ApplicationFiled: February 10, 2022Publication date: August 10, 2023Applicant: Mobile Court Solutions, Inc.Inventors: Richard Joseph SULLIVAN, Ashish VERMA
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Publication number: 20230238444Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.Type: ApplicationFiled: April 3, 2023Publication date: July 27, 2023Applicant: Intel CorporationInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Patent number: 11687163Abstract: A Head Mounted Display (HMD) device includes a display configured to display an augmented reality effect in relation to an Electromyography (EMG) device. The HMD device also includes at least one processor configured to control the display of the augmented reality effect in relation to the EMG device according to a user motion detected by the EMG device. The HMD device may further include a communication unit configured to communicate with the EMG device, and the at least one processor may be configured to receive, from the EMG device via the communication unit, information about data stored on the EMG device. At least some of the received information may be displayed in relation to the EMG device as the augmented reality effect. Information sent from the EMG device to a mobile terminal may be displayed in relation to the EMG device as the augmented reality effect.Type: GrantFiled: February 10, 2020Date of Patent: June 27, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: William Stryker Clausen, Ashish Verma
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Publication number: 20230200079Abstract: A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Chia-Ching Lin, Tanay A. Gosavi, Uygar E. Avci, Sou-Chi Chang, Hai Li, Dmitri Evgenievich Nikonov, Kaan Oguz, Ashish Verma Penumatcha, John J. Plombon, Ian Alexander Young
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Publication number: 20230197836Abstract: Described herein are integrated circuit devices with conductive regions formed from MX or MAX materials. MAX materials are layered, hexagonal carbides and nitrides that include an early transition metal (M) and an A group element (A). MX materials remove the A group element. MAX and MX materials are highly conductive, and their two-dimensional layer structure allows very thin layers to be formed. MAX or MX materials can be used to form several conductive elements of IC circuits, including contacts, interconnects, or liners or barrier regions for contacts or interconnects.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Carl Hugo Naylor, Christopher J. Jezewski, Jeffery D. Bielefeld, Jiun-Ruey Chen, Ramanan V. CHEBIAM, Mauro J. Kobrinsky, Matthew V. Metz, Scott B. Clendenning, Sudurat Lee, Kevin P. O'Brien, Kirby Kurtis Maxey, Ashish Verma Penumatcha, Chelsey Jane Dorow, Uygar E. Avci
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Publication number: 20230189659Abstract: A probabilistic bit (p-bit) comprises a magnetic tunnel junction (MTJ) comprising a free layer whose magnetization orientation randomly fluctuates in the presence of thermal noise. The p-bit MTJ comprises a reference layer, a free layer, and an insulating layer between the reference and free layers. The reference layer and the free layer comprise synthetic antiferromagnets. The use of a synthetic antiferromagnet for the reference layer reduces the amount of stray magnetic field that can impact the magnetization of the free layer and the use of a synthetic antiferromagnet for the free layer reduces stray magnetic field bias on p-bit random number generation. Tuning the thickness of the nonmagnetic layer of synthetic antiferromagnet free layer can result in faster random number generation time relative to a comparable MTJ with a free layer comprising a single-layer ferromagnet.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Punyashloka Debashis, Tanay A. Gosavi, Hai Li, Chia-Ching Lin, Dmitri Evgenievich Nikonov, Kaan Oguz, Ashish Verma Penumatcha, Marko Radosavljevic, Ian Alexander Young
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Patent number: 11653502Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.Type: GrantFiled: December 2, 2019Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Shriram Shivaraman, Seung Hoon Sung, Ashish Verma Penumatcha, Uygar E. Avci
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Patent number: 11646374Abstract: Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.Type: GrantFiled: December 26, 2018Date of Patent: May 9, 2023Assignee: Intel CorporationInventors: Ashish Verma Penumatcha, Tanay Gosavi, Uygar Avci, Ian A. Young
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Patent number: 11646356Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.Type: GrantFiled: January 2, 2019Date of Patent: May 9, 2023Assignee: Intel CorporationInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young