Abstract: The disclosure relates to compositions particularly suited for removing soils from textiles, in particular the removal of oily food soils, oily cosmetic soils, and industrial soils from textiles containing cotton, particularly those comprising one or more of surfactants, and cationic amines, or silicone compounds. Methods of making and using such compounds are also provided.

Abstract: A training data modification system (TDM) for machine learning and related methods. The system comprises a data modifier (DM) configured to perform a modification operation to modify medical training X-ray imagery of a patient. The modification operation causes image structures in the modified medical training imagery. The image structure is representative of a property of i) a medical procedure, ii) an image acquisition operation by an X-ray-based medical imaging apparatus (IA), iii) an anatomy of the patient.

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

Abstract: High-purity Ge channeled N-type transistors include a Si-based barrier material separating the channel from a Ge source and drain that is heavily doped with an N-type impurity. The barrier material may have nanometer thickness and may also be doped with N-type impurities. Because of the Si content, N-type impurities have lower diffusivity within the barrier material and can be prevented from entering high-purity Ge channel material. In addition to Si, a barrier material may also include C. With the barrier material, an N-type transistor may display higher channel mobility and reduced short-channel effects.

Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.

Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.

Abstract: A hotspot accessory camera connectable to a hotspot via a physical connection is provided. The hotspot accessory camera may include edge processing and/or artificial intelligence capabilities for image/video processing of images/video captured by the hotspot accessory camera. The hotspot accessory camera may include a base that accepts a hotspot device, and at least one actuatable arm adapted to hold one or more cameras to effectuate image/video capture.

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

Abstract: A transistor includes a channel layer including a transition metal dichalcogenide (TMD) material, an encapsulation layer on a first portion of the channel layer, a gate electrode above the encapsulation layer, a gate dielectric layer between the gate electrode and the encapsulation layer. The transistor further includes a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate structure is between drain contact and the source contact.

Abstract: A circuit system includes slow running logic circuitry that generates write data and a write command for a write request. The circuit system also includes fast running logic circuitry that receives the write data and the write command from the slow running logic circuitry. The fast running logic circuitry stores the write data and the write command. A host system generates a write response in response to receiving the write command from the fast running logic circuitry. The host system sends the write response to the fast running logic circuitry. The fast running logic circuitry sends the write data to the host system in response to receiving the write response from the host system before providing the write response to the slow running logic circuitry.

Abstract: Storage devices are capable of utilizing receiver devices with native devices configured to support lower voltage supplies for higher read performances. The receiver device may include a current source circuit, first and second stage circuits, and a duty cycle balancer circuit. The first stage circuit may utilize first and second native devices with a threshold voltage (VTH) that enables proper lower voltage operations in saturation at high speeds. The current source stage circuit may utilize a third native device to track a transconductance and provide a reference current that becomes proportional to VTH to maintain tighter gain across process, variation, and temperature (PVT). The second stage circuit may utilize a current folding stage to provide a high gain for faster conversion of intermediate signals. The duty cycle balancer may utilize a fourth native device to balance a rise and fall delay skew across the PVT to maintain tighter duty cycle.

Abstract: A method and apparatus for implementing host-centric antenna control. An apparatus may include a plurality of antennas for wireless transmission and reception, a wireless modem for processing a signal for wireless transmission and reception via the antennas, a processor (host), and an antenna tuner circuitry. The processor is configured to run an antenna tuner software module configured to generate a control signal to configure at least one antenna. The antenna tuner circuitry is configured to switch or tune the at least one antenna based on the control signal. The apparatus may include at least one sensor coupled to the processor. The antenna tuner software module may be configured to generate the control signal based on inputs from the at least one sensor. The antenna tuner software module may be configured to receive RF parameters from the wireless modem and generate the control signal based on the RF parameters.

Abstract: A system and method for unified autodial campaign management, comprising a campaign management console, a data services engine, a traffic shaper, an agent desktop, Control agent desktop, an auto-dialer, and a simple dialer which allows enterprises to conduct unified communications campaigns without differentiating between prior expressed written consent consumers, and those who have not provided prior expressed written consent, to being autodialed or receiving artificial or pre-recorded voice messages, allowing for compliance with regulations regarding such consent without splitting or bifurcating or otherwise hampering communications campaigns for the enterprise customers.

Abstract: A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes Hf1-xZxO2, where 0.33<x<0.5. The first transistor further includes a first gate electrode on the first gate dielectric layer and a first source region and a first drain region on opposite sides of the first gate electrode. The CMOS transistor further includes a second transistor adjacent to the first transistor. The second transistor includes a second gate dielectric layer above a second channel, where the second gate dielectric layer includes Hf1-xZxO2, where 0.5<x<0.99, a second gate electrode on the second gate dielectric layer and a second source region and a second drain region on opposite sides of the second gate electrode.

Abstract: Systems and methods are provided herein to dynamically update content restrictions for multiple users by detecting a first user in the proximity of a media device playing a first content item and detecting a second user entering the proximity of the media device. In response to detecting a second user entering the proximity of the media device and receiving a command from the first user that controls playing the first content, the system modifies a stored relationship between the first user and the second user to track the relationship between the first user and the second user. Thereafter, when the system detects the first user and the second user in the proximity of a media device playing a second content, in response, the system automatically performs an action that controls the playing of the second content (e.g., without user having to issue those commands).

Abstract: Organosilicon chemistry, polymer derived ceramic materials, and methods. Such materials and methods for making polysilocarb (SiOC) and Silicon Carbide (SiC) materials having 3-nines, 4-nines, 6-nines and greater purity. Processes and articles utilizing such high purity SiOC and SiC.

Abstract: A laundry washing machine having an outer casing, a washing tub, a rotatable drum and at least one balancing ring rigidly secured to the rotatable drum. The at least one balancing ring includes a substantially toroidal, annular housing that is rigidly secured to the drum, and has a tubular structure so as to delimit a closed annular inner cavity. A number of balancing masses are accommodated in movable manner inside the annular inner cavity, preferably together with a damping liquid. The annular housing has a substantially frustoconical outer wall segment that is inclined by an angle (?) lower than 90° with respect to the midplane (P) of the annular housing, and a peripheral supporting structure that juts out outwardly from the substantially frustoconical outer wall segment to stably abut against the body of the drum.