Patents by Inventor Ashish .

Ashish . has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130275753
    Abstract: A system and method for verifying credentials are provided. The system includes a credential verification server (102) and a plurality of credential verification local servers (104). The system (100) is configured to receive a request from credential seeker (CS) to verify credentials of a credential owner (CO). The request is forwarded to an appropriate credential verification local server (104) among the plurality of credential verification local servers (104). Thereafter, the credential owner (CO) is notified about the request. Further, instruction is received from the credential owner (CO), wherein the instruction comprises at least one of, denying permission, granting permission to verify credential information as requested by the credential seeker (CS) and granting permission to verify credential information after modifying scope of access to information. Subsequently, access is provided to the credential seeker (CS) to verify credentials based on the instruction received by the credential owner (CO).
    Type: Application
    Filed: June 10, 2012
    Publication date: October 17, 2013
    Applicant: INDRAPRASHTA INSTITUTE OF INFORMATION TECHNOLOGY
    Inventors: Denzil Correa, Ashish Sureka
  • Publication number: 20130274403
    Abstract: Disclosed are oil-extended olefin block copolymer compositions with precipitated silica. The precipitated silica reduces oil-bleed while maintaining composition softness.
    Type: Application
    Filed: December 14, 2011
    Publication date: October 17, 2013
    Inventors: Robert T. Johnston, Ashish Batra, Raymond L. Laakso, JR., Wenbin Liang
  • Publication number: 20130275656
    Abstract: Apparatuses, systems, and methods are disclosed for a key-value store. A method includes encoding a key of a key-value pair into a logical address of a sparse logical address space for a non-volatile medium. A method includes mapping a logical address to a physical location in the non-volatile medium. A method includes storing a value of a key-value pair at a physical location.
    Type: Application
    Filed: August 20, 2012
    Publication date: October 17, 2013
    Applicant: FUSION-IO, INC.
    Inventors: Nisha Talagala, Swaminathan Sundararaman, Bharath Ramsundar, Ashish Batwara
  • Publication number: 20130275438
    Abstract: A method, an apparatus and an article of manufacture for mapping authors across multiple forums. The method includes creating a database that contains publicly observable information pertaining to multiple authors from multiple forums, generating a mapping between at least a first one of the authors from one of the forums and at least a second one of the authors from another of the forums in the database based on a comparison of structured information, unstructured user generated content information and network information, and generating a score of mapping between the first and the second authors by considering a weighted sum of the number of times the structured information, the unstructured user generated content information and the network information match between the first and the second authors.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 17, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jitendra Ajmera, Ashish Verma
  • Publication number: 20130275391
    Abstract: Apparatuses, systems, and methods are disclosed for data expiry. A method includes examining metadata associated with data in a non-volatile recording medium. A method includes expiring data from a non-volatile recording medium in response to metadata indicating that an expiration period for the data has been satisfied.
    Type: Application
    Filed: January 23, 2013
    Publication date: October 17, 2013
    Applicant: FUSION-IO, INC.
    Inventors: Ashish Batwara, Swaminathan Sundararaman, James Peterson, Nisha Talagala
  • Publication number: 20130272096
    Abstract: An audio system comprises an ultrasound sensor array (105) which has a plurality of ultrasound sensor elements, and an audio band array (101) comprising a plurality of audio band elements. The same array of wideband audio transducers may be used for both the ultrasound sensor array (105) and the audio band array (101). An estimator (107) generates a presence characteristic of a user in response to ultrasound signals received from the ultrasound sensor array. The presence characteristic may specifically comprise a position estimate for the user. An audio array circuit (103) generates a directional response for the audio band array (101) by applying weights to individual audio band signals for the audio band elements. A weight circuit (109) determines the weights in response to the presence characteristic. The system may provide improved adaptation of the directivity of the audio band array (101) and specifically does not require the sound source in the audio band to be active for adaptation.
    Type: Application
    Filed: January 2, 2012
    Publication date: October 17, 2013
    Applicant: KONINKLIJKE PHILIPS N.V.
    Inventors: Ashish Vijay Pandharipande, Sriram Srinivasan
  • Patent number: 8560801
    Abstract: Various systems and methods for performing tiering-aware data defragmentation. One method can involve receiving tiering information from a storage device that comprises multiple tiers. The information specifies a tiering attribute and tiering attribute value for the tiers. The method involves establishing zones that have zone attribute values corresponding to the received tiering attribute values. The method then involves storing a given block in a particular zone in response to detecting that a block attribute value of the block corresponds to a zone attribute value for the zone.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: October 15, 2013
    Assignee: Symantec Corporation
    Inventors: Niranjan Pendharkar, Ashish Karnik
  • Patent number: 8560080
    Abstract: Techniques are described, for medical devices that deliver electrical stimulation therapy, for controlling a transition from an initial stimulation location or initial stimulation shape to a user-specified target stimulation location or target stimulation shape in order to limit the rate of change of stimulation. One example method includes receiving, via a programmer for an electrical stimulator, user input indicating a target stimulation zone, and controlling the electrical stimulator to transition electrical stimulation from an initial stimulation zone to the target stimulation zone via one or more intermediate stimulation zones.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: October 15, 2013
    Assignee: Medtronic, Inc.
    Inventors: Steven M. Goetz, Rajeev M. Sahasrabudhe, Jon P. Davis, Brent A. Huhta, Ashish Singal
  • Patent number: 8558862
    Abstract: Sharing computer video in a videoconference. The method may include acquiring video on a computer. The method may also include coding the acquired video on the computer. Transmitting the coded video from the computer to a videoconferencing unit may also be included in the method. Also, the method may include packaging the transmitted video coded on the videoconferencing unit. Furthermore, the method may include transmitting the packaged video to a videoconferencing destination.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: October 15, 2013
    Assignee: LifeSize Communications, Inc.
    Inventors: Hrishikesh G. Kulkarni, Ashish Goyal, Hitesh Chouhan, Raghuram Belur
  • Patent number: 8560922
    Abstract: Bad block management for flash memory including a method for storing data. The method includes receiving a write request that includes write data. A block of memory is identified for storing the write data. The block of memory includes a plurality of pages. A bit error rate (BER) of the block of memory is determined and expanded write data is created from the write data in response to the BER exceeding a BER threshold. The expanded write data is characterized by an expected BER that is lower than the BER threshold. The expanded write data is encoded using an error correction code (ECC). The encoded expanded write data is written to the block of memory.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: John A. Bivens, Michele M. Franceschini, Ashish Jagmohan
  • Publication number: 20130264035
    Abstract: Disclosed are apparatus and methods for material and thermal processing of substrates in a single chamber. In one embodiment, an edge ring is provided. The edge ring includes an annular body having an inner peripheral edge, a first surface, and a second surface opposite the first surface, a first raised member extending substantially orthogonally from the second surface, a second raised member extending from the second surface adjacent the first raised member and separated from the first raised member by a first depression, and a third raised member extending from the second surface adjacent the second raised member and separated by a second depression, the second depression comprising a sloped surface having a reflectivity value that is different than a reflectivity value of the first surface.
    Type: Application
    Filed: March 7, 2013
    Publication date: October 10, 2013
    Inventors: Ashish GOEL, Anantha SUBRAMANI
  • Publication number: 20130268150
    Abstract: A method and powertrain apparatus that predicts a route of travel for a vehicle and uses historical powertrain loads and speeds for the predicted route of travel to optimize at least one powertrain operation for the vehicle.
    Type: Application
    Filed: February 27, 2013
    Publication date: October 10, 2013
    Inventors: Feisel Weslati, Ashish A. Krupadanam
  • Patent number: 8555265
    Abstract: A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: October 8, 2013
    Assignee: Google Inc.
    Inventors: Craig D. Chambers, Ashish Raniwala, Frances J. Perry, Stephen R. Adams, Robert R. Henry, Robert Bradshaw, Nathan Weizenbaum
  • Patent number: 8555002
    Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: October 8, 2013
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
  • Patent number: 8555226
    Abstract: An approach is provided in which a formal verification tool sends a condition signal to a first circuit instance and to a second circuit instance, which are both instances of an electric circuit design. The formal verification tool selects a common input port and sends a first input value to the common input port of the first circuit instance and sends a second input value, which is different than the first input value, to the common input port of the second circuit instance. In turn, the first circuit instance generates a first output value and the second circuit instance generates a second instance value, which are utilized to verify dependencies between the electronic circuit's input ports and output ports.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: October 8, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiushan Feng, Jayanta Bhadra, Ashish Goel
  • Patent number: 8551757
    Abstract: A novel bacterial strain of Bacillus thuringiensis, VBTS 2528, is described. This strain comprises genes encoding Cry1Ac, Cry 1Ca, and Cry2Aa endotoxin proteins. The invention further relates to an insecticidal composition comprising a mixture of VBTS 2528 and to methods for controlling insect pests utilizing VBTS 2528.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: October 8, 2013
    Assignee: Valent BioSciences Corporation
    Inventors: Terry A. Benson, Samun Dahod, Ashish Harihar Dave, Ayyappan Nair, Regina Adams
  • Patent number: 8555024
    Abstract: Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: October 8, 2013
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
  • Patent number: 8553561
    Abstract: Quality of service for mesh networks is described. In embodiment(s), communication data can be prioritized as priority data and/or non-priority data for communication from a source node to a destination node in a mesh network. A first communication route in the mesh network can be determined to communicate the priority data from the source node to the destination node based on a minimum number of intermediate nodes via which the priority data is communicated. Additionally, a second communication route in the mesh network can be determined to communicate the non-priority data from the source node to the destination node based on a highest bit rate to communicate the non-priority data. A time duration to communicate the priority via the first communication route is less than a time duration to communicate the non-priority data via the second communication route.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: October 8, 2013
    Assignee: Marvell International Ltd.
    Inventors: Ronak Anjan Chokshi, Ashish Kumar Shukla, Rajesh Shreeram Bhagwat
  • Patent number: 8553474
    Abstract: Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ibrahim M. Elfadel, Michele Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Mayank Sharma
  • Publication number: 20130261611
    Abstract: A workstation architecture for one or more medical diagnostic instruments is provided using a modular approach. Elements common to operations for the instruments are grouped together as a set of service components that are made available to instrument specific software applications. Application developers can develop software specific to the instrument while accessing the common service components to speed software development. A user interface tool is provided to permit a customized user interface to be developed for the instrument, within a generally consistent interface environment. The resulting user interfaces have a consistent look and behavior among different instrument types to facilitate a simplified and familiar user experience. The common service components provide a broad variety of services that are useful to developers and are easily integrated with instrument specific software. Features such as language variability and secure access points are provided in a distributed environment.
    Type: Application
    Filed: March 17, 2011
    Publication date: October 3, 2013
    Applicant: Siemens Healthcare Diagnostics Inc.
    Inventors: Ashish Dhar, Thinakaran Kesavan