Patents by Inventor Ashish .

Ashish . has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250190221
    Abstract: A disclosed method may include initializing a deep learning recommendation model (DLRM) comprising a plurality of embedding tables, each embedding table comprising a plurality of embeddings. The method may also include receiving input data associated with accessing embeddings from the plurality of embedding tables and applying a parallelization strategy to process the plurality of embedding tables, the parallelization strategy configured to improve performance by distributing computational workloads and optimizing memory access. The method may also include processing the embeddings based on the input data in accordance with the parallelization strategy, the processing comprising aggregating embeddings accessed from the plurality of embedding tables. The method may also include generating, for further processing, output data based on the processed embeddings. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 9, 2024
    Publication date: June 12, 2025
    Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.
    Inventors: Krishnakumar Nair, Meenakshi Arunachalam, John Kalamatianos, Rishabh Jain, Varun Agrawal, Avinash Chandra Pandey, Siddappa Yallappa Karabannavar, Ashish Sirasao, Elliott Delaye
  • Publication number: 20250193779
    Abstract: A circuit arrangement includes a preprocessing circuit configured to obtain context information related to a user location, a learning circuit configured to determine a predicted user movement based on context information related to a user location to obtain a predicted route and to determine predicted radio conditions along the predicted route, and a decision circuit configured to, based on the predicted radio conditions, identify one or more first areas expected to have a first type of radio conditions and one or more second areas expected to have a second type of radio conditions different from the first type of radio conditions and to control radio activity while traveling on the predicted route according to the one or more first areas and the one or more second areas.
    Type: Application
    Filed: August 20, 2024
    Publication date: June 12, 2025
    Inventors: Shahrnaz AZIZI, Biljana BADIC, John BROWNE, Dave CAVALCANTI, Hyung-Nam CHOI, Thorsten CLEVORN, Ajay GUPTA, Maruti GUPTA HYDE, Ralph HASHOLZNER, Nageen HIMAYAT, Simon HUNT, Ingolf KARLS, Thomas KENNEY, Yiting LIAO, Christopher MACNAMARA, Marta MARTINEZ TARRADELL, Markus Dominik MUECK, Venkatesan NALLAMPATTI EKAMBARAM, Niall POWER, Bernhard RAAF, Reinhold SCHNEIDER, Ashish SINGH, Sarabjot SINGH, Srikathyayani SRIKANTESWARA, Shilpa TALWAR, Feng XUE, Zhibin YU, Robert ZAUS, Stefan FRANZ, Uwe KLIEMANN, Christian DREWES, Juergen KREUCHAUF
  • Publication number: 20250189945
    Abstract: Various systems and methods are presented regarding generating executable computer code/instructions from input files, whereby the input files may be an image file (e.g., JPEG, PDF, etc.). The image file can be digital capture of a sequence of instructions such as a graphical representation comprising a ladder diagram, a function block diagram, a sequential function chart, etc. P&ID and suchlike can also be submitted to the system. Code generated from the input files can be enhanced by application of historical data comprising pertinent subroutines, and suchlike. Further, an entity can be prompted to provide further information in the event of the input file does not provide all of the content.
    Type: Application
    Filed: December 12, 2023
    Publication date: June 12, 2025
    Inventors: ADRIAN D PANTEA, Michael J. Ohlsen, Anthony Carrara, Christopher S. Hays, Allen Rosu, Ashish Anand, Christopher E. Stanek, Fabiano Fernandes
  • Publication number: 20250192756
    Abstract: A validation circuit is placed in vicinity of a critical path for testing the critical path. The validation circuit receives test data from the control circuit for testing the critical path. The test data is indicative of a delay value that is associated with the critical path. The validation circuit generates multiple setup signals and an enable signal to facilitate the testing of the critical path based on the test data. The validation circuit generates a first test signal based on the enable signal, and a second test signal based on the first test signal and the setup signals. The second test signal is a delayed version of the first test signal. The validation circuit compares the first test signal and the second test signal. A mismatch between the first test signal and the second test signal indicates deviation from the delay value.
    Type: Application
    Filed: January 29, 2024
    Publication date: June 12, 2025
    Inventors: Ashish Goel, Ajay Sharma, Ruchi Bora, Umesh Pratap Singh
  • Publication number: 20250192794
    Abstract: A continuous-time analog-to-digital converter circuit includes an input to which an analog input signal can be applied; an analog delay element being interconnected between the input and a first summation node; and an ADC-DAC path interconnected between the input and the first summation node. The ADC-DAC path digitizes the analog input signal and to reconvert the digitized analog input signal back to analog and to subtract the reconverted signal at the first summation node, the ADC-DAC path includes a switch interconnected between the input and a sub ADC the switch samples the analog input with a specified sampling rate. A sub DAC is interconnected between the sub ADC and the first summation node and delays of the analog delay element and the ADC-DAC path are matched by means of a delay control element. An output at the first summation node is filtered by a filter element. An output of the filter element is sampled by the specified sampling rate.
    Type: Application
    Filed: December 5, 2024
    Publication date: June 12, 2025
    Inventors: Kamlesh Singh, Sushil Kumar Gupta, Ashish Ashok Panpalia, Pankaj Agrawal
  • Publication number: 20250192792
    Abstract: A continuous-time analog-to-digital converter circuit includes an input configured to receive an analog input signal; a delay element with a specified time delay, the delay element functionally connected between the input and a first summation node; a ADC-DAC path with a sub ADC and a sub DAC connected between the input and the first summation node. The ADC-DAC path is configured to digitize the analog input signal and to reconvert the digitized signal to analog domain and to subtract it at the first summation node. An output of the first summation node is filtered by means of a continuous-time filter and an output of the continuous-time filter is clocked by a specified sampling rate. A backend ADC is configured to digitize the clocked output of the analog filter and to connect the clocked output to a second summation node. An output is obtained by a summation of the output of the backend ADC and an output of a digital filter is connected to the sub ADC.
    Type: Application
    Filed: December 5, 2024
    Publication date: June 12, 2025
    Inventors: Kamlesh Singh, Sushil Kumar Gupta, Ashish Ashok Panpalia, Pankaj Agrawal
  • Publication number: 20250189620
    Abstract: A communication system reserves a first portion of a transmitted frame for communication symbols and a second portion of the transmitted frame of symbols for a plurality of radar sensing symbols. The communication symbols are of variable length.
    Type: Application
    Filed: December 12, 2023
    Publication date: June 12, 2025
    Inventors: Vinicius Oliari Couto Dias, Nauman Farooq Kiyani, Ashish Pandharipande, Wilhelmus Johannes van Houtum
  • Publication number: 20250188239
    Abstract: Disclosed herein are manufacturing/casting processes for the preparation of a foam.
    Type: Application
    Filed: February 13, 2025
    Publication date: June 12, 2025
    Inventors: Ashish MITRA, Jens SOMMER-KNUDSEN
  • Publication number: 20250191364
    Abstract: A system for video anomaly detection is configured to extract, from a set of input frames of the input video, input appearance features indicative of the appearance of the object in a frame, input size features indicative of the size of the object in the scene, input location features indicative of the location of the object in the scene, and input trajectory features indicative of a trajectory of the object tracked in a set of frames of the input video. The system combines the input appearance features, the input size features, the input location features, and the input trajectory features to produce an input feature vector and compares the input feature vector with each of the exemplars extracted from the normal video to determine the smallest distance from the input feature vector to its closest exemplar. The system declares the anomaly when the smallest distance is greater than a threshold.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 12, 2025
    Applicant: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Michael Jones, Ashish Singh, Erik Learned-Miller
  • Publication number: 20250191497
    Abstract: Disclosed herein a neurosurgical simulator for training of various tasks involved in Endoscopic Endonasal Transsphenoidal Surgery, composed of a human head model comprising an anterior portion including a nose part, and a posterior portion detachably mounted on an inclined base part; a plurality of apertures on the nose part for insertion of an endoscope and an instrument for manipulation; said inclined base part placed at an inclination to mimic a patient position during endo-nasal surgery; wherein said base part comprises a protruded platform having slots to create male-female connection with corresponding a plurality of protrusions provided under one or more activity plates; wherein said activity plates are so designed to train various tasks including pick-place, drilling, incising, punching/grasping and precision movements around the anatomical structures.
    Type: Application
    Filed: March 8, 2023
    Publication date: June 12, 2025
    Inventors: Ramandeep SINGH, Rajdeep SINGH, Ashish SURI
  • Publication number: 20250193097
    Abstract: In certain embodiments, a computer-implemented method includes aggregating data messages related to a device that are transmitted over a network within a defined aggregation period into a single data message; comparing the single data message to previously-aggregated data from a preceding aggregation period stored in a data store to determine whether the single data message differs from the previously-aggregated data; storing, in response to determining that the single data message differs from the previously-aggregated data, the single data message to the data store; and regenerating a state timeline of the device using the stored data in the data store.
    Type: Application
    Filed: March 6, 2024
    Publication date: June 12, 2025
    Inventors: Uttej Goparaju, Sharan Chaitanya Potturu, Dheeraj Dinesh Bapat, Ashish Prabhakar, Tathagata Roy
  • Publication number: 20250187017
    Abstract: A cartridge for use with chemical or biological analysis systems, as well as methods of using the same, is provided. The cartridge may include a floating microfluidic plate that is held in the cartridge using one or more floating support brackets that incorporate gaskets that may seal against fluidic ports on the microfluidic plate. The floating support brackets may include indexing features that may align the microfluidic plate with the seals.
    Type: Application
    Filed: February 11, 2025
    Publication date: June 12, 2025
    Inventors: David Elliott Kaplan, Anthony John de Ruyter, Richard Alan Kelley, Ashish Kumar
  • Publication number: 20250192099
    Abstract: Integrated circuit package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce a die to a substrate clearance and related fabrication methods are disclosed. The IC package includes die interconnects coupled to first metal pad(s) of respective metal interconnects of a metallization layer of the substrate to provide support and signal routing paths. To reduce clearance between the die and the substrate and consequently the height of the IC package, a second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is coupled to the first metal pad(s). Solder is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate. When the solder is heated to form the solder joint, the solder flows along the reduced cross-sectional area of the second, additional metal pad(s).
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Inventors: Ashish Alawani, Abhishek Shrikant Agarwal, Heun Gun Shin
  • Patent number: 12328372
    Abstract: One or more computing devices, systems, and/or methods for determining activity patterns based upon user activity and/or performing operations based upon the activity patterns are provided. For example, activity performed using a communication interface associated with a user account may be detected. The activity may be analyzed to determine an activity pattern associated with a first set of conditions. The activity pattern may be stored in a user profile associated with the user account. The user profile may comprise a plurality of activity patterns. Each activity pattern of the plurality of activity patterns may be associated with a set of conditions of a plurality of sets of conditions. It may be determined that the first set of conditions are met. Responsive to determining that the first set of conditions are met, one or more operations associated with the activity pattern may be performed.
    Type: Grant
    Filed: March 25, 2024
    Date of Patent: June 10, 2025
    Assignee: Yahoo Assets LLC
    Inventors: Mohit Goenka, Ashish Khushal Dharamshi, Nikita Varma, Gnanavel Shanmugam
  • Patent number: 12327773
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: January 17, 2024
    Date of Patent: June 10, 2025
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
  • Patent number: 12325028
    Abstract: A cartridge for use with chemical or biological analysis systems, as well as methods of using the same, is provided. The cartridge may include a floating microfluidic plate that is held in the cartridge using one or more floating support brackets that incorporate gaskets that may seal against fluidic ports on the microfluidic plate. The floating support brackets may include indexing features that may align the microfluidic plate with the seals.
    Type: Grant
    Filed: February 11, 2025
    Date of Patent: June 10, 2025
    Assignee: Illumina, Inc.
    Inventors: David Elliott Kaplan, Anthony John de Ruyter, Richard Alan Kelley, Ashish Kumar
  • Patent number: 12328621
    Abstract: Embodiments are directed towards embodiments are directed toward systems and methods for user plane function (UPF) and network slice load balancing within a 5G network. Example embodiments include systems and methods for load balancing based on current UPF load and thresholds that depend on UPF capacity; UPF load balancing using predicted throughput of new UE on the network based on network data analytics; UPF load balancing based on special considerations for low latency traffic; UPF load balancing supporting multiple slices, maintaining several load-thresholds for each UPF and each slice depending on the UPF and network slice capacity; and UPF load balancing using predicted central processing unit (CPU) utilization and/or predicted memory utilization of new UE on the network based on network data analytics.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: June 10, 2025
    Assignee: DISH Wireless L.L.C.
    Inventors: Mehdi Alasti, Kazi Bashir, Ash Khamas, Ashish Bansal, Siddhartha Chenumolu
  • Patent number: 12328428
    Abstract: A device for upscale filtering video data includes one or more processors configured to generate a number of upscaled pixels that is an integer multiple of one half of a size of a filter used to upscale filter the video data. The device may then store the remaining pixels to be used to upscale filter a subsequent, right-neighboring block. In this manner, the device may avoid generating upscaled pixels that will result in being unaligned with the block and that may not be output due to being unaligned.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: June 10, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Vikrant Mahajan, Sandeep Nellikatte Srivatsa, Ashish Mishra, Apoorva Nagarajan, Divya Goswami
  • Patent number: 12328361
    Abstract: The present invention relates to communications methods and apparatus for session load balancing among session processing entities. An exemplary method embodiment includes the steps of receiving from a first device at a Signaling Front End Load Balancer (SLB) a first session initiation request destined for a second device; making a first session load balancing decision at the SLB with respect to the received first session initiation request; transmitting the first session initiation request to a first Session Border Controller (SBC) worker based on the first load balancing decision, the first SBC worker being one of a plurality of SBC workers forming a cluster of SBC workers, making a session mismatch determination at the first SBC worker with respect to a first session corresponding to the first session initiation request; and when the session mismatch determination is that a session mismatch has occurred notifying the SLB of the session mismatch.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: June 10, 2025
    Assignee: Ribbon Communications Operating Company, Inc.
    Inventors: Tolga Asveren, Shivakumar Venkataraman, Amol Sudhir Gogate, Justin Hart, Ashish Sharma
  • Patent number: 12326927
    Abstract: To automatically onboard network functions to a credential vault, a orchestration processor actuates establishment of an cluster account for a network cluster, and actuates a cluster configuration of a processor of the vault to enable authentication of a network cluster. For each of a plurality of network functions associated with the network cluster, the orchestration processor generates an identifier, sets values for parameters of an initialization parameter set, actuates assignment of access permissions for a code address on a memory of the vault, actuates assignment of elevated access permissions for a credential address on the vault memory, and actuates association of the network function with a cluster account of the network cluster. The vault memory thereby defines credential addresses each corresponding to a respective network function.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: June 10, 2025
    Assignee: RAKUTEN SYMPHONY, INC.
    Inventors: Akashdeep Chopra, Manish Kumar, Ashish Madan