Patents by Inventor Ashish .

Ashish . has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250111115
    Abstract: A formal verification tool is used to assess the performance of a hardware design for an integrated circuit to complete a set of tasks. The tool monitors one or more control signals and/or data signals of an instantiation of the hardware design to identify start and completion of a symbolic task by the instantiation of the hardware design, the symbolic task representing the set of tasks. A number of cycles between the start and the completion of the symbolic task is counted, and it is verified that one or more formal properties related to the counted number of cycles are true for the hardware design. An indication of whether or not each of the one or more formal properties was successfully verified is outputted, the indication providing an exhaustive assessment of the performance of the instantiation of the hardware design in completing the set of tasks.
    Type: Application
    Filed: December 12, 2024
    Publication date: April 3, 2025
    Inventors: Ashish Darbari, Iain Singleton
  • Publication number: 20250110841
    Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. The control logic identify a subset of memory blocks of one or more memory planes that pass a program count operation associated with a last programming level of the set of programming levels. The control logic further terminates execution of the programming operation on the one or more memory planes associated with the subset of memory blocks.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Inventors: Lu Tong, Ashish Ghai, Chai Chuan Yao, Ekamdeep Singh, Lakshmi Kalpana Vakati, Sheng Huang Lee, Matthew Ivan Warren, Dheeraj Srinivasan, Jeffrey Ming-Hung Tsai
  • Patent number: 12266570
    Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Kimin Jun, Souvik Ghosh, Willy Rachmady, Ashish Agrawal, Siddharth Chouksey, Jessica Torres, Jack Kavalieros, Matthew Metz, Ryan Keech, Koustav Ganguly, Anand Murthy
  • Patent number: 12266218
    Abstract: A method and computing apparatus for extracting information from a document are provided. The method includes receiving a document, extracting data from the document, assigning the document to a category from among a predetermined plurality of categories based on a result of the extracted data, and generating a structured output by formatting the extracted data based on the assigned category.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: April 1, 2025
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Vrajesh Ricky Amin, Ashish Singla, Samantha Zucker, Dana Marie Niblack, Stephen Musacchia, Lawrence Fata, Albert Naclerio, Hozefa Shabbir Zariwala, Anirudh Hegde, Yasser Thamby, Saquib Ahmad
  • Patent number: 12263176
    Abstract: The present invention relates to stable injectable compositions comprising meloxicam or its pharmaceutically acceptable salts, solvates, or hydrates thereof, wherein the composition is provided in a sealed container, e.g., an ampoule, vial and pre-filled syringe. Further, the present invention relates to a stable injectable solution comprising meloxicam or its pharmaceutically acceptable salts, solvates, or hydrates thereof, suitable for subcutaneous, intravenous or intramuscular administration. The invention relates to methods for manufacturing stable injectable solutions of meloxicam. The present invention further relates to a method of treating pain by parenterally administering to a patient in need thereof a composition comprising a stable solution of meloxicam, wherein said solution provides rapid onset of action for pain relief compared to a reference composition.
    Type: Grant
    Filed: December 15, 2023
    Date of Patent: April 1, 2025
    Assignee: SLAYBACK PHARMA LLC
    Inventors: Ashish Anilrao Dubewar, Sumitra Ashokkumar Pillai, Pradeep Kumar Kare, Kumar Swamy Ummiti, Shanker Mamidi, Raghavender Rao Kategher
  • Patent number: 12265648
    Abstract: The present invention allows a CEC system to automatedly track the use, storage, access, and modification of sensitive information/data in the system through desktop monitoring. Further, through desktop, video, and audio monitoring of CSRs the system can automatedly determine the improper use, access, storage, and modification of sensitive information by implementing sensitive data use rules that allow a system to be specialized for the user. Finally, the system can automatedly determine and implement violation actions for the improper use, storage, access, and manipulation of sensitive information. This provides an intelligent system capable of locating all sensitive data in the system and regulating the use, access, and storage of sensitive data in the system.
    Type: Grant
    Filed: April 2, 2024
    Date of Patent: April 1, 2025
    Assignee: Verint Americas, Inc
    Inventors: Michael Johnston, Neil Eades, Ashish Sood
  • Patent number: 12265789
    Abstract: Techniques are described herein that are capable of creating a language-agnostic computer program repair engine generator. A context-free grammar is annotated to identify token(s) that are likely to be included in or excluded from a computer program in a manner that violates the context-free grammar. A language-agnostic computer program repair engine generator is created that is configured to generate a parser. The repair engine generator is configured to create a repair engine that: converts the candidate string into repaired strings that neither violate the context-free grammar nor violate a criterion for a valid computer program; calculates differences between the candidate string and the respective repaired strings; and replaces the candidate string with a designated repaired string based at least in part on the difference between the designated repaired string and the candidate string being less than or equal to a difference threshold.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: April 1, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rohan Jayesh Bavishi, José Pablo Cambronero Sánchez, Anna Fariha, Sumit Gulwani, Vu Minh Le, Ivan Radicek, Daniel Galen Simmons, Ashish Tiwari
  • Patent number: 12266720
    Abstract: Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Chelsey Dorow, Kevin O'Brien, Sudarat Lee, Kirby Maxey, Ashish Verma Penumatcha, Tanay Gosavi, Patrick Theofanis, Chia-Ching Lin, Uygar Avci, Matthew Metz, Shriram Shivaraman
  • Patent number: 12265969
    Abstract: Systems, methods, and computer-readable storage media utilized in math-based currency (MBC) exchange utilizing MBC transaction guarantees. One method includes receiving, from a merchant point of sale (POS) terminal, a payment reimbursement request comprising a guarantee identifier associated with an MBC transfer. The method further includes determining, utilizing the guarantee identifier, transaction information. The method further includes determining, utilizing the transaction information, the guarantee identifier is associated with a failed transaction based on accessing and analyzing a plurality of disputed transactions on an MBC blockchain. The method further includes, in response to identifying the failed transaction, initiating an MBC payment from the financial computing system to an MBC address of a merchant. The method further includes providing, to the merchant POS terminal, a payment confirmation.
    Type: Grant
    Filed: March 11, 2024
    Date of Patent: April 1, 2025
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Ashish Kurani, Wayne Barakat, Martin Barrs, Dominik Vltavsky
  • Patent number: 12265921
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for milestone prediction of fuel and chemical usage. An example apparatus includes one or more memories comprising computer readable instructions; one or more processors to execute the computer readable instructions to determine a current amount of fuel required without halt and a current fuel consumption rate for a machine during a harvesting event in a field based on a first amount of fuel required without halt, a first fuel consumption rate, and real time information from sensors of the machine, and determine a real time amount of fuel required based on the current amount of fuel required without halt, the current fuel consumption rate, and a halt time for the machine during the harvesting event, the one or more processors to use the real time amount of fuel required to schedule fuel delivery for the machine.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: April 1, 2025
    Assignee: DEERE & COMPANY
    Inventors: Ashish Apte, Arikatla Vishnu Vardhan Reddy, Vishal Dobariya, Pallavi Bhargava, Hrishikesh H Tupe
  • Patent number: 12266712
    Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Kevin O'Brien, Chelsey Dorow, Kirby Maxey, Carl Naylor, Tanay Gosavi, Sudarat Lee, Chia-Ching Lin, Seung Hoon Sung, Uygar Avci
  • Patent number: 12265908
    Abstract: Systems, apparatuses, and methods for achieving higher cache hit rates for machine learning models are disclosed. When a processor executes a given layer of a machine learning model, the processor generates and stores activation data in a cache subsystem a forward or reverse manner. Typically, the entirety of the activation data does not fit in the cache subsystem. The processor records the order in which activation data is generated for the given layer. Next, when the processor initiates execution of a subsequent layer of the machine learning model, the processor processes the previous layer's activation data in a reverse order from how the activation data was generated. In this way, the processor alternates how the layers of the machine learning model process data by either starting from the front end or starting from the back end of the array.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 1, 2025
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Benjamin Thomas Sander, Swapnil Sakharshete, Ashish Panday
  • Patent number: 12265958
    Abstract: A computer-implemented method includes: transmitting, by a mobile device, to a mobile wallet computer system, an indication that a user of the mobile device wishes to perform a mobile wallet transaction to transfer funds to a merchant; receiving, by the mobile device, an amount of merchant rewards that are available for the user to use at the merchant; displaying, by the mobile device, the amount of merchant rewards; receiving, by the mobile device, an indication that the user wishes to apply at least a portion of the available rewards to the transaction; and, transmitting, to a merchant computer system, the indication that the user wishes to apply at least a portion of the available rewards to the transaction. The merchant rewards are applied to the transaction prior to submitting the transaction to a card network computer system, and no physical rewards card is used to complete the transaction.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: April 1, 2025
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Ashish Bhoopen Kurani, Nikolai Stroke
  • Publication number: 20250103440
    Abstract: A method for performing a backup operation, the method comprising receiving a backup request for an asset, partitioning, based on available capacity in a proxy infrastructure, a plurality of slices of the asset into a plurality of backup sessions, wherein each backup session comprises a separate portion of the slices, wherein the plurality of slices are associated with a queue, sending a first reservation request to the proxy infrastructure, wherein the first reservation request specifies the plurality of backup sessions, making a first determination that a first portion of the plurality of backup sessions was successfully reserved and that a second portion of the plurality of backup sessions was unsuccessfully reserved, sending a request to initiate the first portion of the plurality of backup sessions on the proxy infrastructure, and sending the second portion of the plurality of backup sessions to the queue based on the first determination.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Inventors: Upanshu Singhal, Shelesh Chopra, Ashish Kumar
  • Publication number: 20250103437
    Abstract: A method for performing a backup operation, the method comprising receiving a backup operation request for an asset, partitioning a plurality of slices of the asset into a plurality of backup sessions, wherein each backup session comprises a separate portion of the plurality of slices, sending a first backup request to a proxy manager to initiate a backup session of the plurality of backup sessions, wherein initiating the backup session comprises: instantiating a container on the one compute node, wherein the backup session operates within the container, receiving a notification that one of the plurality of slices in the backup session has been processed, and sending, based on the notification, a second backup request to the proxy manager to add a new slice to the backup session, wherein the new slice is associated with a second asset.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Inventors: Upanshu Singhal, Shelesh Chopra, Ashish Kumar
  • Publication number: 20250104767
    Abstract: A failure of a flash memory device of multiple flash memory devices positioned on corresponding printed circuit boards is detected by a storage device controller detachably coupled to the flash memory devices and positioned on an interposer board. An indication that the flash memory device has failed is generated. A replacement of the flash memory device with a subsequent flash memory device is detected. In response to detecting the replacement, data stored on the flash memory device is rebuilt and stored on the subsequent flash memory device.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: ALEXANDER NOBLE, ASHISH KARKARE, ETHAN MILLER
  • Publication number: 20250107174
    Abstract: Neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. In an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. The intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Inventors: Siddharth CHOUKSEY, Jack T. KAVALIEROS, Stephen M. CEA, Ashish AGRAWAL, Willy RACHMADY
  • Publication number: 20250103439
    Abstract: A method for performing a backup operation, the method comprising receiving a backup operation request for an asset, identifying a queue comprising the plurality of slices, wherein each slice references a separate portion of the asset, sending a first backup request to a proxy manager to instantiate a container for each of a plurality of backup sessions, wherein each backup session corresponds to a slice of the plurality of slices, receiving, from the proxy manager, a notification that one of the number of backup sessions is complete and a corresponding container has been torn down, making a second determination that there is an additional slice on a second queue associated with a second asset, and sending, based on the second determination, a backup request to the proxy manager to instantiate a new container for the additional slice associated with the second asset.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Inventors: Upanshu Singhal, Shelesh Chopra, Ashish Kumar
  • Publication number: 20250103448
    Abstract: A hardware reconfiguration system for first and second devices is in a lock-step configuration using a comparator that provides a lock-step error indication. The system includes at least one register that stores a lock-step threshold. The system also includes a lock-step monitor configured to compare a count of occurrences of the lock-step error indication from the comparator with the lock-step threshold. When the lock-step threshold is reached, the lock-step monitor is configured to enter a repair state to determine which one of the first and second devices is operating correctly and reconfigure operation into a split-lock mode to resume operation using the one of the first and second devices that is operating correctly.
    Type: Application
    Filed: September 3, 2024
    Publication date: March 27, 2025
    Inventors: Ashish Kumar, Arjun Muddaiah
  • Publication number: 20250103976
    Abstract: A system for optimizing labor resources at a facility. The system includes a memory configured to store a first optimization model and a second optimization model. Where the first optimization model, when executed by a control circuit, determines optimal shift patterns for full-time employee schedules and fixed part-time employee schedules over a period of time. Where the second optimization model, when executed by the control circuit, determines headcounts and variable part-time shifts. The system further includes an electronic device configured to execute an application stored in a local memory of the electronic device, the application when executed causes the control circuit to output one or more staffing recommendation levels displayable on the electronic device.
    Type: Application
    Filed: September 20, 2024
    Publication date: March 27, 2025
    Inventors: Kartheek Ponnuru, Jingrui Li, Prachi A. Patki, Sophia Burathoki, Harshavardhan R. Nannur, Ajay Sharma, Ashish Raj, Mohith Varma