Patents by Inventor Ashish .

Ashish . has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250117693
    Abstract: Embodiments provide for improved model maintenance utilizing third-party workspaces. Some embodiments receive data artifact(s) associated with training of a machine learning model, generate model keyword(s) based on the data artifact(s), and store the machine learning model linked with the model keyword(s). Some embodiments receive data artifact(s), generate an embedded representation based on the data artifact(s), and store the embedded representation of the machine learning model in an embedding space. The stored data is then searchable to identify relevant models for deployment.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 10, 2025
    Inventors: Vivek BHADAURIA, Ashish MISHRA, Anand DHANDHANIA, Vasant MANOHAR, Carlos W. MORATO
  • Publication number: 20250115291
    Abstract: A method for detecting early life failure of an electrical connection of a power harness for a steering system of a vehicle including, using a processor configured to execute instructions, obtaining a resistance measurement associated with an electrical power delivery system including the electrical connection, obtaining historical resistance data obtaining at least one limit based on at least one of the historical resistance data and a functional limit, detecting an early life failure of the electrical connection based on a comparison between the resistance measurement and the at least one limit, performing at least one action in response to detecting the early life failure.
    Type: Application
    Filed: January 25, 2024
    Publication date: April 10, 2025
    Inventors: Ashish Verma, Julie A. Kleinau, David M. Williams, Peter D. Schmitt, Christopher J. Sommer, Kevin L. Derry
  • Publication number: 20250118064
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating an output image. In one aspect, one of the methods includes generating the output image intensity value by intensity value according to a generation order of pixel-color channel pairs from the output image, comprising, for each particular generation order position in the generation order: generating a current output image representation of a current output image, processing the current output image representation using a decoder neural network to generate a probability distribution over possible intensity values for the pixel—color channel pair at the particular generation order position, wherein the decoder neural network includes one or more local masked self-attention sub-layers; and selecting an intensity value for the pixel—color channel pair at the particular generation order position using the probability distribution.
    Type: Application
    Filed: October 11, 2024
    Publication date: April 10, 2025
    Inventors: Noam M. Shazeer, Lukasz Mieczyslaw Kaiser, Jakob D. Uszkoreit, Niki J. Parmar, Ashish Teku Vaswani
  • Patent number: 12271268
    Abstract: A method for performing a backup operation, the method comprising receiving a backup operation request for an asset, partitioning a plurality of slices of the asset into a plurality of backup sessions, wherein each backup session comprises a separate portion of the plurality of slices, sending a first backup request to a proxy manager to initiate a backup session of the plurality of backup sessions, wherein initiating the backup session comprises: instantiating a container on the one compute node, wherein the backup session operates within the container, receiving a notification that one of the plurality of slices in the backup session has been processed, and sending, based on the notification, a second backup request to the proxy manager to add a new slice to the backup session, wherein the new slice is associated with a second asset.
    Type: Grant
    Filed: September 22, 2023
    Date of Patent: April 8, 2025
    Assignee: Dell Products L.P.
    Inventors: Upanshu Singhal, Shelesh Chopra, Ashish Kumar
  • Patent number: 12271259
    Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 8, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Ashish Darbari, Iain Singleton
  • Patent number: 12268610
    Abstract: A stemless prosthetic shoulder joint may include a prosthetic humeral head and a stemless base. The stemless base may include a collar and an anchor extending from the collar intended to anchor the base into the proximal humerus. The base may include a proximal collar having a proximal surface and a bone-engaging surface opposite the proximal surface. The collar may have a superior portion and an inferior portion, the superior portion defining an arc shape and the inferior portion defining a substantially triangular shape.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: April 8, 2025
    Assignee: Howmedica Osteonics Corp.
    Inventors: Daniel E. Sapio, Ashish Mehta, Andrew J. Nelson, Bernhard Hofstaetter, Sunny Shorabh
  • Patent number: 12273569
    Abstract: The present disclosure is generally directed to media systems configured to receive and play live media content. In particular, methods and systems are provided for a multi-screen content playback experience for time shifted live stream content. Systems and methods are provided herein for generating for display a catch-up video (e.g., a segment of a live stream stored as URLs on a local device during the time the live stream was interrupted) in a picture-in-picture (PIP) window, and generating the PIP catch-up window and the live window for simultaneous display.
    Type: Grant
    Filed: October 26, 2023
    Date of Patent: April 8, 2025
    Assignee: Adeia Guides Inc.
    Inventors: Ashish Gupta, Vaibhav Gupta, Rohit Dhiman
  • Patent number: 12271272
    Abstract: A method for performing a backup operation, the method comprising receiving a backup operation request for an asset, identifying a queue comprising the plurality of slices, wherein each slice references a separate portion of the asset, sending a first backup request to a proxy manager to instantiate a container for each of a plurality of backup sessions, wherein each backup session corresponds to a slice of the plurality of slices, receiving, from the proxy manager, a notification that one of the number of backup sessions is complete and a corresponding container has been torn down, making a second determination that there is an additional slice on a second queue associated with a second asset, and sending, based on the second determination, a backup request to the proxy manager to instantiate a new container for the additional slice associated with the second asset.
    Type: Grant
    Filed: September 22, 2023
    Date of Patent: April 8, 2025
    Assignee: Dell Products L.P.
    Inventors: Upanshu Singhal, Shelesh Chopra, Ashish Kumar
  • Patent number: 12271670
    Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: April 8, 2025
    Assignee: Xilinx, Inc.
    Inventors: Rajvinder S. Klair, Dhiraj Kumar Prasad, Saikat Bandyopadhyay, Ashish Kumar Jain, Shiyao Ge, Tapodyuti Mandal, Miti Joshi
  • Patent number: 12273484
    Abstract: A system and method for centralized multichannel campaign management using digital consent acquisition, comprising: a campaign manager console, configured to allow an enterprise, such as a contact center, to create, configure, monitor, and deploy outbound call campaigns; a list manager configured to store, retrieve, create, and transform lists of numbers which can be used in the call campaign; a digital consent manager configured integrate with a plurality of digital channels in order to transmit to and receive messages from a consumer device in order to obtain consumer consent for a telephone call prior to a call being made by one or more auto-dialer systems; and a consumer device comprising a software application configured to connect with the digital consent manager via one or more integrated digital channels to so that the user of the consumer device can provide consent for a call to be received.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: April 8, 2025
    Assignee: ACQUEON TECHNOLOGIES INC.
    Inventors: Ashok Raj Susairaju, Ashish Koul
  • Publication number: 20250111242
    Abstract: Various systems and methods providing a platform that facilitates creating, managing, and searching for documents, such as medical documents, and the evaluation of medical workflows, are described. In some embodiments, the systems and methods utilize machine learning models (e.g., large language models, or LLMs), such as ML models that employ reinforcement learning from human feedback (RLHF), or similar reinforcement learning models, to enhance and/or optimize operations and processes provided or supported by the platform, such as search queries, scenario, generation, and information retrieval operations, and so on.
    Type: Application
    Filed: October 2, 2024
    Publication date: April 3, 2025
    Inventors: Tulasee Rao CHINTHA, Ashish Advani, Steve Pickette
  • Publication number: 20250113599
    Abstract: Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Rachel A. Steinhardt, Kevin P. O'Brien, Ashish Verma Penumatcha, Carl Hugo Naylor, Kirby Maxey, Pratyush P. Buragohain, Chelsey Dorow, Mahmut Sami Kavrik, Wouter Mortelmans, Marko Radosavljevic, Uygar E. Avci, Matthew V. Metz
  • Publication number: 20250113577
    Abstract: Embodiments of the disclosure advantageously provide semiconductor devices, fin field effect transistors (FinFETs) in particular, and methods of manufacturing such devices having improved effective capacitance (Ceff). The FinFETs include a gate structure in which airgaps are provided by recessing a high-k material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high-k dielectric layer and improving effective capacitance (Ceff) of the device.
    Type: Application
    Filed: September 23, 2024
    Publication date: April 3, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Veeraraghavan S. Basker, Sai Hooi Yeong, Ashish Pal, El Mehdi Bazizi, Benjamin Colombeau, Balasubramanian Pranatharthiharan
  • Publication number: 20250111121
    Abstract: An apparatus and method for efficiently managing performance and power consumption among replicated functional blocks of an integrated circuit despite different circuit behavior amongst the functional blocks due to manufacturing variations. An integrated circuit includes multiple replicated functional blocks, each being a semiconductor die with a corresponding communication fabric for routing packets. A second functional block placed between a first functional block and a third functional block routes packets to destinations from at least the first and the third functional blocks, and provides higher performance than the first and the third functional blocks due to semiconductor manufacturing variations. A power manager assigns a single power supply voltage to the replicated functional blocks, and assigns a target clock frequency to the first and the third functional blocks. The power manager assigns another clock frequency greater than the target clock frequency to the second functional block.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Ashish Jain, Lakshminarayana Pappu
  • Publication number: 20250110480
    Abstract: A method of a device supporting augmented reality (AR) or virtual reality (VR), includes: detecting an occurrence of at least one sensory discomfort to a user when the user uses the device supporting the AR or the VR; determining a source internet-of-thing (IoT) device triggering the occurrence of the at least one sensory discomfort to the user by an operational state of the source IoT device; providing at least one suggestion to the user though a user interface of the device; and adjusting, based on a response of the user to the provided at least one suggestion, the operational state of the source IoT device.
    Type: Application
    Filed: June 10, 2024
    Publication date: April 3, 2025
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ashish BHATT, Kushlam CHOWRASIYA, Sahil GAUTAM, Aman Chetan FRAMEWALA
  • Publication number: 20250109399
    Abstract: The present disclosure relates to compositions of matter and assay methods used to detect one or more target nucleic acids of interest in a sample. The compositions and methods provide signal boost upon detection of target nucleic acids of interest in less than one minute and in some instances instantaneously at ambient temperatures down to 16° C. or less, without amplification of the target nucleic acids yet allowing for massive multiplexing, high accuracy and minimal non-specific signal generation.
    Type: Application
    Filed: September 16, 2024
    Publication date: April 3, 2025
    Inventors: Anurup Ganguli, Ashish Pandey, Ariana Mostafa, Jacob Berger
  • Publication number: 20250110813
    Abstract: Techniques and mechanisms for dynamically changing a distribution of credits with which initiator agents of a network access a shared target resource of the network. In various embodiments, a target agent and multiple initiator agents are coupled to each other via a switched network, and further via a credit management bus (CMB). The target agent manages a credit-based scheme according to which the initiator agents share access to a target resource. Communications via the CMB enable the target agent to determine, during a runtime of the network, whether a given initiator agent has been allocated an excessive number of credits, or an insufficient number of credits. In another embodiments, the target agent changes the distribution of credits to the initiator agents by allocating credits via the CMB.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Rahul Pal, Ashish Gupta, William Bainbridge
  • Publication number: 20250110525
    Abstract: A computer-implemented method for enabling a feature of a semiconductor device can include receiving, by at least one processor of a semiconductor device, a command to enable a feature of the semiconductor device. The method can also include burning, by the at least one processor and in response to the command, an electronic fuse of the semiconductor device. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Paul Blinzer, Maulik Ojas Mankad, Victor Ignatski, Ashish Jain, Gia Phan, Ranjeet Kumar
  • Publication number: 20250112122
    Abstract: Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: INTEL CORPORATION
    Inventors: Kevin P. O'Brien, Paul Gutwin, David L. Kencke, Mahmut Sami Kavrik, Daniel Chanemougame, Ashish Verma Penumatcha, Carl Hugo Naylor, Kirby Maxey, Uygar E. Avci, Tristan A. Tronic, Chelsey Dorow, Andrey Vyatskikh, Rachel A. Steinhardt, Chia-Ching Lin, Chi-Yin Cheng, Yu-Jin Chen, Tyrone Wilson
  • Publication number: 20250113540
    Abstract: Techniques and mechanisms for providing gate dielectric structures of a transistor. In an embodiment, the transistor comprises a thin channel structure which comprises one or more layers of a transition metal dichalcogenide (TMD) material. The channel structure forms two surfaces on opposite respective sides thereof, wherein the surfaces extend to each of two opposing edges of the channel structure. A composite gate dielectric structure comprises first bodies of a first dielectric material, wherein the first bodies each adjoin a different respective one of the two opposing edges, and variously extend to each of the surfaces two surfaces. The composite gate dielectric structure further comprises another body of a second dielectric material other than the first dielectric material. In another embodiment, the other body adjoins one or both of the two surfaces, and extends along one or both of the two surfaces to each of the first bodies.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Carl H. Naylor, Rachel Steinhardt, Mahmut Sami Kavrik, Chia-Ching Lin, Andrey Vyatskikh, Kevin O’Brien, Kirby Maxey, Ashish Verma Penumatcha, Uygar Avci, Matthew Metz, Chelsey Dorow