Memory device and methods for its fabrication
A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.
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The present invention generally relates to semiconductor memory devices and to methods for their fabrication, and more particularly relates to nonvolatile memory devices, especially dual storage node memory devices and to method for their fabrication.
BACKGROUNDMemory storage capacity has been enhanced by fabricating dual storage node nonvolatile semiconductor memory cells that are able to store two bits of data in each memory cell. Such cells store information in a charge storage layer with charge storage locations at opposite sides of a control gate. If the charge storage layer is continuous between the storage locations, there is a potential problem of charge diffusion between the storage locations resulting in problems of data retention and reliability. The charge storage locations can be separated in a dual storage node device by utilizing an undercut structure such as disclosed in U.S. Pat. No. 6,861,307. Such a device, however, results in an undercut feature that is difficult to fill easily and reliably without leaving an air void. Additionally, especially as device dimensions shrink, it is difficult in such a structure to achieve the desired effective oxide thicknesses in the storage locations and in the gate insulator separating the storage locations.
Accordingly, it is desirable to provide a nonvolatile semiconductor memory device having isolation between dual storage nodes. In addition, it is desirable to provide a semiconductor memory device having enhanced data retention. It is also desirable to provide a nonvolatile memory device that is programmable by channel hot electron injection and that can be erased by Fowler-Nordheim tunneling. It is also desirable to provide methods for fabricating an undercut structure nonvolatile memory device having improved data retention. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
BRIEF SUMMARYNonvolatile semiconductor memory devices are provided that includes dual memory nodes and that can be scaled down to small dimensions. In accordance with one embodiment of the invention a memory device comprises first and second layered stacks formed on a semiconductor substrate. Each of the layered stacks comprises spatially sequential layers of oxide, nitride, polycrystalline silicon, nitride, and oxide. A gate insulator is positioned between the first and second layered stacks, and a control gate overlies the layered stacks and the gate insulator.
Methods are provided for fabricating a memory device. In accordance with one embodiment of the invention a method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.
The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein
The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
As illustrated in
The method continues, as illustrated in
In accordance with one embodiment of the invention the method continues as illustrated in
After etching undercut regions 40 and 41, a tunnel dielectric layer 44 is formed on the surface of semiconductor substrate 22 and simultaneously a dielectric layer 45 is formed on the underside 47 and exposed side surfaces of gate electrode 32 as illustrated in
As illustrate in
Following the filling of void 48 with charge storage layer 52, the charge storage layer and dielectric layer 46 are removed from the top and sidewalls of gate electrode 32. If the charge storage layer is silicon, the silicon can be converted to a silicon oxide by thermal oxidation and the silicon oxide can be removed by wet etching with a dilute HF solution. This is a more controllable removal method than direct etching of the silicon layer. If dielectric layer 46 is silicon nitride or silicon rich silicon nitride, that layer can be removed by etching in phosphoric acid (H3PO4). The partially fabricated memory storage cell appears as illustrated in
The method continues, in accordance with an embodiment of the invention, with the deposition of a layer of spacer forming material (not illustrated) such as a layer of silicon oxide or silicon nitride. The layer of spacer forming material is anisotropically etched, for example by reactive ion etching, to form sidewall spacers 60 and 62 at the sidewalls of gate electrode 32 as illustrated in
As illustrated in
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiment or exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the invention as set forth in the appended claims and the legal equivalents thereof.
Claims
1. A method for fabricating a memory device in and on a silicon substrate, the method comprising the steps of:
- forming a gate oxide layer on a surface of the silicon substrate;
- depositing and patterning a layer of polycrystalline silicon to form a polycrystalline silicon gate electrode overlying the gate oxide layer, the polycrystalline silicon gate electrode having first and second opposing edges;
- etching the gate oxide layer to form first and second undercut regions of the gate oxide layer at the first and second opposing edges, respectively, of the polycrystalline silicon gate electrode;
- in each of the first and second undercut regions: thermally oxidizing the silicon substrate and the polycrystalline silicon gate electrode to form a first silicon oxide layer at the surface of the silicon substrate and a second silicon oxide layer on the polycrystalline silicon gate electrode; depositing a layer of nitride on the first silicon oxide layer and on the second silicon oxide layer, leaving a void between the layer of nitride on the first silicon oxide layer and the layer of nitride on the second silicon oxide layer; and depositing a layer comprising polycrystalline silicon to fill the void;
- implanting conductivity determining ions into the silicon substrate to form first and second bit lines in alignment with the first and second opposing edges, respectively; and
- depositing and patterning a layer of conductive material to form a word line electrically coupled to the polycrystalline silicon gate electrode.
2. The method of claim 1 wherein the step of implanting comprises the steps of:
- forming sidewall spacers on the polycrystalline silicon gate electrode; and
- implanting conductivity determining ions using the sidewall spacers as an ion implantation mask to form the bit lines.
3. The method of claim 1 wherein the step of depositing a layer of nitride comprises the step of depositing a layer of silicon nitride.
4. The method of claim 1 wherein the step of depositing a layer of nitride comprises the step of depositing a layer of silicon rich silicon nitride.
5. The method of claim 1 wherein the step of depositing a layer comprising polycrystalline silicon comprises the step of depositing a layer of impurity doped polycrystalline silicon.
6. The method of claim 1 wherein the step of forming a gate oxide layer comprises the step of forming a silicon dioxide layer having a first effective oxide thickness and wherein the steps of thermally oxidizing, depositing a layer of nitride, and depositing a layer comprising polycrystalline silicon comprise forming a layered structure having a composite effective oxide thickness less than the first effective oxide thickness.
7. A method for fabricating a memory device in and on a semiconductor substrate, the method comprising the steps of:
- forming a gate insulator and a gate electrode overlying the semiconductor substrate;
- etching the gate insulator to form an undercut opening beneath an edge of the gate electrode;
- filling the undercut opening with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride;
- impurity doping a region of the semiconductor substrate to form a bit line aligned with the gate electrode; and
- depositing and patterning a conductive layer to form a word line coupled to the gate electrode.
8. The method of claim 7 wherein the step of filling the undercut opening comprises the steps of:
- forming a first oxide layer on the semiconductor substrate and a second oxide layer on the gate electrode;
- forming a non-oxide dielectric layer on the first oxide layer and on the second oxide layer; and
- depositing the charge trapping layer on the non-oxide dielectric layer.
9. The method of claim 8 wherein the step of forming a non-oxide layer comprises the step of forming a layer comprising a material selected from the group consisting of silicon nitride and silicon rich silicon nitride.
10. The method of claim 7 wherein the step of impurity doping comprises the step of implanting conductivity determining ions into the semiconductor substrate, the method further comprising the step of forming sidewall spacers on the gate electrode for use as ion implantation masks.
11. A method for fabricating a memory device in and on a semiconductor substrate, the method comprising the steps of:
- forming a gate insulator overlying the semiconductor substrate, the gate insulator characterized by a first effective oxide thickness;
- depositing and patterning a gate electrode material overlying the gate insulator to form a gate electrode;
- etching the gate insulator to form an undercut opening beneath an edge of the gate electrode and exposing an underside portion of the gate electrode; and
- filling the undercut opening with a layered structure comprising a charge trapping layer sandwiched between dielectric layers, the layered structure having a second effective oxide thickness less than the first effective oxide thickness.
12. The method of claim 11 wherein the step of filling comprises the steps of:
- forming a layer of first dielectric material on the semiconductor substrate and on the underside portion of the gate electrode;
- depositing a layer of second dielectric material on the layer of first dielectric material; and
- depositing the charge trapping layer on the layer of second dielectric material.
13. The method of claim 12 wherein the semiconductor substrate comprises a silicon substrate, the gate electrode comprises polycrystalline silicon, and wherein the step of forming a layer of first dielectric material comprises the step of thermally oxidizing the silicon substrate and the polycrystalline silicon to form silicon dioxide layers.
14. The method of claim 12 wherein the step of depositing a layer of second dielectric material comprises the step of depositing a layer of material selected from the group consisting of silicon nitride and silicon rich silicon nitride.
15. The method of claim 14 wherein the step of depositing the charge trapping layer comprises the step of depositing a layer of silicon to fill a void left by the step of depositing a layer of material.
Type: Grant
Filed: Apr 20, 2006
Date of Patent: Oct 7, 2008
Assignee: Spansion LLC (Sunnyvale, CA)
Inventors: Chungho Lee (Sunnyvale, CA), Ashot Melik-Martirosian (Sunnyvale, CA), Hiroyuki Kinoshita (San Jose, CA), Kuo-Tung Chang (Saratoga, CA), Amol Joshi (Sunnyvale, CA), Meng Ding (Sunnyvale, CA)
Primary Examiner: Richard A. Booth
Attorney: Ingrassia Fisher & Lorenz, P.C.
Application Number: 11/409,361
International Classification: H01L 21/8247 (20060101);