Patents by Inventor Ashutosh Malshe

Ashutosh Malshe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210042181
    Abstract: A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Inventors: Vamsi Pavan Rayaprolu, Harish R. Singidi, Kishore Kumar Muchherla, Ashutosh Malshe, Xiangang Luo
  • Patent number: 10915444
    Abstract: A processing device in a memory system determines whether a first data block of a plurality of data blocks on the memory component satisfies a first threshold criterion pertaining to a first number of the plurality of data blocks having a lower amount of valid data than a remainder of the plurality of data blocks. Responsive to the first data block satisfying the first threshold criterion, the processing device determines whether the first data block satisfies a second threshold criterion pertaining to a second number of the plurality of data blocks having been written to more recently than the remainder of the plurality of data blocks. Responsive to the first data block satisfying the second threshold criterion, the processing device determines whether a rate of change of an amount of valid data on the first data block satisfies a third threshold criterion.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 9, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Sampath K. Ratnam, Ashutosh Malshe, Peter Sean Feeley
  • Patent number: 10915400
    Abstract: One or more blocks from a pool of storage area blocks of the memory component are allocated to a first set of purposed blocks. First write operations are performed to write first data to first data stripes at user blocks of the memory component. Whether the blocks in the first set of purposed blocks satisfy a condition indicating that the first set of purposed blocks are to be retired is determined. Responsive to the blocks in the first set of purposed blocks satisfying the condition, one or more other blocks from the pool of storage area blocks of the memory component are allocated to a second set of purposed blocks. Second write operations are performed to write second data to second data stripes at the user blocks of the memory component.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Sampath K. Ratnam
  • Publication number: 20210034274
    Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 4, 2021
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Harish R. Singidi, Gianni S. Alsasua
  • Publication number: 20210035649
    Abstract: A processing device in a memory system determines that data stored in a first block of a plurality of blocks of a memory component satisfies a first threshold criterion pertaining to an age of the data. Responsive to the data stored in the first block satisfying the first threshold criterion, the processing device maintains a first counter to track a number of read operations performed on the first block. The processing device further determines that the data stored in the first block does not satisfy the first threshold criterion, and in response, maintains a second counter to track a number of read operations performed on a super block comprising the plurality of blocks.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 4, 2021
    Inventors: Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Harish R. Singidi, Gianni S. Alsasua
  • Publication number: 20210035642
    Abstract: A request to perform a write operation at a memory component can be received. A destination block of the memory component to store data of the write operation can be determined. A voltage pulse can be applied to the destination block that places a memory cell of the destination block at a voltage level associated with a high voltage state. Responsive to applying the voltage pulse to the destination block, an erase operation for the destination block can be performed to change the voltage level of the memory cell from the high voltage state to a low voltage state. A write operation can be performed to write the data to the destination block that is at the low voltage state.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe
  • Publication number: 20210027846
    Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 28, 2021
    Inventors: Ashutosh Malshe, Harish Reddy Singidi, Kishore Kumar Muchherla, Michael G. Miller, Sampath Ratnam, Xu Zhang, Jie Zhou
  • Publication number: 20200411083
    Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Retano Padilla, JR.
  • Publication number: 20200411117
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Reddy Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
  • Publication number: 20200371690
    Abstract: A system includes a memory component and a processing device to determine an amount of data stored at a region of a memory component and determine, based on the amount of data stored in the region of the memory component. The processing device determines a frequency to perform an operation on one or more memory cells of the region of the memory component. The processing device performs the operation on the one or more memory cells at the frequency to maintain the one or more memory cells of the region of the memory component in a first state associated with a first error rate for data stored at the one or more memory cells. The first error rate is less than a second error rate associated with a second state of the one or more memory cells.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Ashutosh Malshe, Kishore Kumar Muchherla
  • Publication number: 20200371870
    Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Xiangang Luo, Vamsi Pavan Ravaprolu, Ashutosh Malshe
  • Publication number: 20200365219
    Abstract: Disclosed in some examples, are systems, methods, machine-readable mediums, and NAND memory devices which utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.
    Type: Application
    Filed: August 6, 2020
    Publication date: November 19, 2020
    Inventors: Harish Reddy Singidi, Scott Anthony Stoller, Jung Sheng Hoei, Ashutosh Malshe, Gianni Stephen Alsasua, Kishore Kumar Muchherla
  • Patent number: 10818361
    Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Harish Reddy Singidi, Kishore Kumar Muchherla, Michael G. Miller, Sampath Ratnam, Xu Zhang, Jie Zhou
  • Publication number: 20200335172
    Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Micheal G. Miller
  • Publication number: 20200319827
    Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, JR.
  • Patent number: 10796745
    Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Renato Padilla, Jr.
  • Publication number: 20200293203
    Abstract: A memory block of a non-volatile memory device is identified. The memory block has a first region and a second region, where a storage density of the first region is larger than the second region. Data is programmed at the first region of the memory block. An attribute of the memory block based on a sensor is received during programming of the data at the memory block. The attribute characterizes the data being programmed at the first region. The attribute is stored at a volatile during programming of the data at the memory block. The attribute is stored on a memory page of the second region responsive to the programming of the data at the first region being complete.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
  • Patent number: 10777284
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Reddy Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
  • Patent number: 10770156
    Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.
    Type: Grant
    Filed: May 18, 2019
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi
  • Publication number: 20200278814
    Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Peter Sean Feeley, Ashutosh Malshe, Renato Padilla, JR., Kishore Kumar Muchherla, Sampath Ratnam