Abstract: A processing device, operatively coupled with the memory device, is configured to determine a first error rate associated a first set of pages of a plurality of pages of a data unit of a memory device, and a second error rate associated with a second set of pages of the plurality of pages of the data unit, determine a first pattern of error rate change for the data unit based on the first error rate and the second error rate, and responsive to determining that the first pattern of error rate change corresponds to a predetermined second pattern of error rate change, perform an action pertaining to defect remediation with respect to the data unit.

Abstract: A method includes receiving, by a processing device, an indication that a media management operation performed with respect to a block of a memory sub-system satisfies a performance condition, wherein the block maintains first data stored using a first write mode, in response to receiving the indication, determining, by the processing device, that a cache block of a cache area of the memory sub-system satisfies an endurance condition, wherein the cache block maintains second data stored using a second write mode, and changing, by the processing device, a write mode for the cache block from the second write mode to the first write mode responsive to determining that the cache block satisfies the endurance condition.

Abstract: A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.

Abstract: NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.

Abstract: An amount of threshold voltage distribution shift is determined. The threshold voltage distribution shift corresponds to an amount of time after programming of a reference page of a block of a memory device. A program-verify voltage is adjusted based on the amount of threshold voltage distribution shift to obtain an adjusted program-verify voltage. Using the adjusted program-verify voltage, a temporally subsequent page of the block is programmed at a time corresponding to the amount of time after the programming of the reference page.

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Abstract: A first set of host data items are programmed to first memory pages residing at a first region of a memory sub-system. A second set of host data items are programmed to second memory pages residing at the first region. A determination is made that a sequence at which the first set of host data items and the second set of host data items are programmed does not correspond to a target sequence associated with the memory sub-system. One or more of the first set of host data items are copied from one or more first memory pages to a second region of the memory sub-system that is allocated to store host data items initially programmed to first memory pages at the memory sub-system. One or more of the second set of host data items are copied from one or more second memory pages to a third region of the memory sub-system to store host data items that are programmed to second pages at the memory sub-system.

Abstract: A system can include a memory device, and a processing device, operatively coupled with the memory device, to perform operations of writing a first portion of data to one or more complete translation units of the memory device using a first number of logical levels per memory cell and writing a second portion of the data to one or more incomplete translation units of the memory device using the first number of logical levels per memory cell. The operations can also include writing a third portion of the data to one or more complete translation units of the memory device using a second number of logical levels per memory cell that exceeds the first number of logical levels per memory cell.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a first data integrity check on memory pages of a first set of wordlines of the memory device; performing a second data integrity check on memory pages of a second set of wordlines comprising a plurality of wordlines from the first set of wordlines; identifying, among the first set of wordlines and the second set of wordlines, a wordline having a first data state metric value obtained from the first data integrity check equal to a second data state metric value obtained from the second data integrity check; and performing a third data integrity check on a third set of wordlines comprising at least one wordline from the first set of wordlines, wherein the third data integrity check excludes the identified wordline.

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

Abstract: A method includes determining respective valid translation unit counts of a block of non-volatile memory cells over a period of time, determining a rate of change of the respective valid translation unit counts of the block of non-volatile memory cells over the period of time, comparing the rate of change of the valid translation unit counts to a bin transition rate, and based on comparing the rate of change of the valid translation unit counts to the bin transition rate, performing a media management operation on the block of non-volatile memory cells.

Abstract: A method includes obtaining a first operation execution time corresponding to an operation performed on a page of a first data unit of a memory device, determining whether the first operation execution time satisfies a condition that is based on a second operation execution time, wherein the second operation execution time is indicative of lack of defect in at least a second data unit of the memory device, and responsive to determining that the first operation execution time satisfies the condition that is based on the second operation execution time, initiating a defect scan operation of at least a subset of pages of the first data unit.

Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device. The processing device further generates a parity page for data stored in the page of the data unit and associates the parity page with parity data associated with the data unit. Responsive to determining that a first size of the parity data is larger than a first threshold size, the processing device compresses the parity data. Responsive to determining that a second size of the compressed parity data is larger than a second threshold size, the processing device releases at least a subset of the parity data corresponding to a subset of the data that is free from defects.

Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

Abstract: A request to perform a secure erase operation for a memory component can be received. A voltage level of a pass voltage that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied during a program operation to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can exceed the pass voltage applied to the unselected wordlines of the memory component during the read operation.

Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

Abstract: A method includes identifying, by a processing device, a common pool of blocks comprising a first plurality of blocks allocated to system data and a second plurality of blocks allocated to user data; determining whether user data has been written to the second plurality of blocks within a threshold period of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold period of time, allocating a block from the second plurality of blocks to the first plurality of blocks.

Abstract: A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.