Patents by Inventor Ashutosh Misra

Ashutosh Misra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031951
    Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: June 8, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Slegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
  • Patent number: 10985778
    Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Siegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
  • Patent number: 10944423
    Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Siegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
  • Publication number: 20200321976
    Abstract: Compressing data includes hashing a first token length of an incoming data steam into a hash table, where the first token length includes a plurality of bytes. A second token length of the incoming data stream may be hashed into the hash table. The second token may be larger than the first token length and includes the plurality of bytes. The method may further include automatically comparing which token length enabled more efficient data compression, and automatically adjusting at least one of the first and second token lengths based on the comparison.
    Type: Application
    Filed: April 2, 2019
    Publication date: October 8, 2020
    Inventors: Bulent ABALI, Ashutosh MISRA, Girish G. KURUP, Deepankar BHATTACHARJEE, Matthias KLEIN
  • Publication number: 20200301604
    Abstract: Various embodiments are provided for managing multiport banked memory arrays in a computing system by a processor. One or more conflicts may be eliminated in a multiport banked memory array upon receiving one or more write operations, read operations, or a combination thereof according to a selected priority and access protocol.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 24, 2020
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent ABALI, Ashutosh Misra, Hubertus FRANKE, Matthias KLEIN, Deepankar Bhattacharjee, Girish Kurup
  • Publication number: 20200293377
    Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.
    Type: Application
    Filed: January 14, 2020
    Publication date: September 17, 2020
    Inventors: Timothy Slegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
  • Publication number: 20200295780
    Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Inventors: Timothy Slegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
  • Publication number: 20200295781
    Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.
    Type: Application
    Filed: January 14, 2020
    Publication date: September 17, 2020
    Inventors: Timothy Slegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
  • Publication number: 20200272565
    Abstract: A system architecture is provided and includes an on-chip coherency unit, a processing unit, an accelerator and dedicated wiring. The processing unit is communicative with the on-chip coherency unit via a first interface. The accelerator is communicative with the on-chip coherency unit via a second interface. The accelerator is configured to be receptive of a request to execute lossless data compression or decompression from the processing unit and to responsively execute the lossless data compression or decompression faster than the processing unit. The processing unit and the accelerator are directly communicative by way of the dedicated wiring.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Inventors: Matthias Klein, Ashutosh Misra, Girish Gopala Kurup
  • Patent number: 10756758
    Abstract: Various embodiments are provided for length-limited Huffman encoding in a data compression accelerator in a computing environment by a processor. Symbol counts of a plurality of symbols in compressed data may be normalized and manipulated according to a maximum code length limiting operation such that those of the plurality of symbols having a least frequent symbol count have a symbol count equal to a maximum code length of a Huffman tree.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, Ashutosh Misra, Matthias Klein
  • Patent number: 10754781
    Abstract: Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in each of a plurality of performance modes. The method further includes choosing a performance mode based on the monitoring. Thereafter, using the performance mode for a predetermined amount of time. Each of the plurality of performance modes is a branch prediction mode.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Ashutosh Misra, Brian R. Prasky
  • Patent number: 10715174
    Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for reducing a latch count required for symbol sorting when generating a dynamic Huffman table. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. The accelerator further includes a Huffman encoder communicatively coupled to the LZ77 compressor. The Huffman encoder includes a bit translator. The accelerator further includes an output buffer communicatively coupled to the Huffman encoder.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, Ashutosh Misra, Suneel Pusarla
  • Patent number: 10693493
    Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for reducing a latch count required for symbol sorting when generating a dynamic Huffman table. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. The accelerator further includes a Huffman encoder communicatively coupled to the LZ77 compressor. The Huffman encoder includes a bit translator. The accelerator further includes an output buffer communicatively coupled to the Huffman encoder.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, Ashutosh Misra, Suneel Pusarla
  • Patent number: 10673460
    Abstract: An aspect includes a system architecture that includes a processing unit, an accelerator, a main source buffer, a main target buffer, and a memory block. The main source buffer stores a first part of a source symbol received from an external source. The main target buffer stores an output symbol received from the accelerator. The memory block includes an overflow source buffer that stores the first part of the source symbol received from the main source buffer. The accelerator fetches the first part of the source symbol stored in the overflow source buffer and a second part of the source symbol stored in the main source buffer, and converts the first and second parts of the source symbol together into the output symbol. The second part of the source symbol includes a part of the source symbol not included in the first part of the source symbol.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Girish Gopala Kurup, Matthias Klein, Anthony Thomas Sofia, Jonathan D. Bradbury, Ashutosh Misra, Christian Jacobi, Deepankar Bhattacharjee
  • Patent number: 10585626
    Abstract: A system and method to manage a non-universal encoder and a universal encoder for compression of data include receiving the data. The data includes symbols. The method also includes subdividing the data into a first set of data blocks and a second set of data blocks and generating a non-universal encoder using the first set of data blocks. The non-universal encoder includes first codes. Each of the first codes corresponds to one of the symbols in the first set of data blocks only and at least one of the first codes includes fewer bits than the symbol corresponding to the at least one of the first codes. The method further includes compressing the second set of data blocks using at least the non-universal encoder.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan Bradbury, Matthias Klein, Ashutosh Misra, Anthony Sofia
  • Patent number: 10409609
    Abstract: A system, method and computer program product for maintaining an age and validity of entries in a structure associated with a processor is disclosed. An age tracking matrix is created for the structure. Each row of the age tracking matrix corresponds to an entry of the structure and each column of the age tracking matrix corresponds to an entry of the structure. When initiating an entry: a row corresponding to the entry is determined and a field in the determined row that is on a diagonal of the matrix is marked. For each other field in the determined row, the values that are in a diagonal field that is in a same column of the field are copied into the field. A relative age of the entries is determined by counting a number of marked fields in a column of the age tracking matrix.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Ashutosh Misra, Anthony Saporito
  • Publication number: 20190179572
    Abstract: A system and method to manage a non-universal encoder and a universal encoder for compression of data include receiving the data. The data includes symbols. The method also includes subdividing the data into a first set of data blocks and a second set of data blocks and generating a non-universal encoder using the first set of data blocks. The non-universal encoder includes first codes. Each of the first codes corresponds to one of the symbols in the first set of data blocks only and at least one of the first codes includes fewer bits than the symbol corresponding to the at least one of the first codes. The method further includes compressing the second set of data blocks using at least the non-universal encoder.
    Type: Application
    Filed: December 7, 2017
    Publication date: June 13, 2019
    Inventors: Jonathan Bradbury, Matthias Klein, Ashutosh Misra, Anthony Sofia
  • Patent number: 10097600
    Abstract: A method for analyzing streaming data includes providing a streaming accumulator comprising an addition module and two multiplexers, receiving one or more data streams, continuously calculating a set of basic statistical elements, receiving a request to calculate a set of statistical descriptors, calculating the set of statistical descriptors, and providing the set of statistical descriptors. An apparatus for analyzing streaming data includes a first multiplexer configured to receive a first summation, a second summation, and a current data item, and forward the first summation on cycles 1 and 3, forward the second summation on cycle 4, and forward the current data item on cycle 2, a second multiplexer configured to receiver the second summation, a third summation, and a previous data item, and forward the previous data item on cycles 1 and 3, forward the second summation on cycle 4, and forward the third summation on cycle 2.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Suchismita Banerjee, Girish G. Kurup, Ashutosh Misra, Niranjan Vaish
  • Publication number: 20180246811
    Abstract: Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in each of a plurality of performance modes. The method further includes choosing a performance mode based on the monitoring. Thereafter, using the performance mode for a predetermined amount of time. Each of the plurality of performance modes is a branch prediction mode.
    Type: Application
    Filed: February 27, 2017
    Publication date: August 30, 2018
    Inventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Ashutosh Misra, Brian R. Prasky
  • Patent number: 10033778
    Abstract: A method for analyzing streaming data includes providing a streaming accumulator comprising an addition module and two multiplexers, receiving one or more data streams, continuously calculating a set of basic statistical elements, receiving a request to calculate a set of statistical descriptors, calculating the set of statistical descriptors, and providing the set of statistical descriptors. An apparatus for analyzing streaming data includes a first multiplexer configured to receive a first summation, a second summation, and a current data item, and forward the first summation on cycles 1 and 3, forward the second summation on cycle 4, and forward the current data item on cycle 2, a second multiplexer configured to receiver the second summation, a third summation, and a previous data item, and forward the previous data item on cycles 1 and 3, forward the second summation on cycle 4, and forward the third summation on cycle 2.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Suchismita Banerjee, Girish G. Kurup, Ashutosh Misra, Niranjan Vaish