Patents by Inventor Ashutosh Misra
Ashutosh Misra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240135236Abstract: Apparatus and methods for intelligently classifying unclassified transactions are provided. A program may receive a set of transaction data. The program may divide the set into a training set of classified transactions and a test set of unclassified transactions. The program may analyze the training set to generate a document term matrix. The program may analyze the test set and compare the analyzed terms to the document term matrix to predict a classification. The program may iterate to a pre-determined level of confidence in the prediction and assign a classification to a particular transaction.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Inventors: Krishna Reddy Mandala, Ananya Bhattacharyya, Ashutosh Misra, Marc Halsted, David Joa
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Patent number: 11663119Abstract: One or more units of decompressed data of a plurality of units of decompressed data is written to a target location for subsequent writing to memory. The plurality of units of decompressed data includes a plurality of symbol outputs and has associated therewith a plurality of decompression headers. A determination is made that the subsequent writing to memory of at least a portion of another unit of decompressed data to be written to the target location is to be stalled. A symbol start position of the other unit of decompressed data and a decompression header of a selected unit of the one or more units of decompressed data written to the target location are provided to a component of the computing environment. The decompression header is used for the subsequent writing of the other unit of decompressed data to memory.Type: GrantFiled: May 29, 2020Date of Patent: May 30, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deepankar Bhattacharjee, Girish Gopala Kurup, Ashutosh Misra, Puja Sethia
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Patent number: 11223369Abstract: Compressing data includes hashing a first token length of an incoming data steam into a hash table, where the first token length includes a plurality of bytes. A second token length of the incoming data stream may be hashed into the hash table. The second token may be larger than the first token length and includes the plurality of bytes. The method may further include automatically comparing which token length enabled more efficient data compression, and automatically adjusting at least one of the first and second token lengths based on the comparison.Type: GrantFiled: April 2, 2019Date of Patent: January 11, 2022Assignee: International Business Machines CorporationInventors: Bulent Abali, Ashutosh Misra, Girish G. Kurup, Deepankar Bhattacharjee, Matthias Klein
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Patent number: 11216212Abstract: Various embodiments are provided for managing multiport banked memory arrays in a computing system by a processor. One or more conflicts may be eliminated in a multiport banked memory array upon receiving one or more write operations, read operations, or a combination thereof according to a selected priority and access protocol.Type: GrantFiled: March 19, 2019Date of Patent: January 4, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bulent Abali, Ashutosh Misra, Hubertus Franke, Matthias Klein, Deepankar Bhattacharjee, Girish Kurup
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Publication number: 20210374049Abstract: One or more units of decompressed data of a plurality of units of decompressed data is written to a target location for subsequent writing to memory. The plurality of units of decompressed data includes a plurality of symbol outputs and has associated therewith a plurality of decompression headers. A determination is made that the subsequent writing to memory of at least a portion of another unit of decompressed data to be written to the target location is to be stalled. A symbol start position of the other unit of decompressed data and a decompression header of a selected unit of the one or more units of decompressed data written to the target location are provided to a component of the computing environment. The decompression header is used for the subsequent writing of the other unit of decompressed data to memory.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Inventors: Deepankar Bhattacharjee, Girish Gopala Kurup, Ashutosh Misra, Puja Sethia
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Patent number: 11188503Abstract: Compression of data is facilitated by locating matches within the data to be compressed. A first technique is used to determine whether there is at least one matching string in the data to be compressed, and a second technique, different from the first technique, is used to determine whether there is at least one matching record in the data to be compressed. Based on there being at least one matching string in the data to be compressed, at least one indication of the at least one matching string is provided to an encoder to facilitate compression of the data. Further, based on there being at least one matching record in the data to be compressed, at least one indication of the at least one matching record is provided to the encoder to facilitate compression of the data. It is transparent to the encoder whether the first technique or the second technique is used to provide one or more matches.Type: GrantFiled: February 18, 2020Date of Patent: November 30, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthias Klein, Damir Anthony Jamsek, Bulent Abali, Ashutosh Misra, Preetham M. Lobo
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Patent number: 11119928Abstract: A system architecture is provided and includes an on-chip coherency unit, a processing unit, an accelerator and dedicated wiring. The processing unit is communicative with the on-chip coherency unit via a first interface. The accelerator is communicative with the on-chip coherency unit via a second interface. The accelerator is configured to be receptive of a request to execute lossless data compression or decompression from the processing unit and to responsively execute the lossless data compression or decompression faster than the processing unit. The processing unit and the accelerator are directly communicative by way of the dedicated wiring.Type: GrantFiled: February 27, 2019Date of Patent: September 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthias Klein, Ashutosh Misra, Girish Gopala Kurup
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Publication number: 20210255999Abstract: Compression of data is facilitated by locating matches within the data to be compressed. A first technique is used to determine whether there is at least one matching string in the data to be compressed, and a second technique, different from the first technique, is used to determine whether there is at least one matching record in the data to be compressed. Based on there being at least one matching string in the data to be compressed, at least one indication of the at least one matching string is provided to an encoder to facilitate compression of the data. Further, based on there being at least one matching record in the data to be compressed, at least one indication of the at least one matching record is provided to the encoder to facilitate compression of the data. It is transparent to the encoder whether the first technique or the second technique is used to provide one or more matches.Type: ApplicationFiled: February 18, 2020Publication date: August 19, 2021Inventors: Matthias Klein, Damir Anthony Jamsek, Bulent Abali, Ashutosh Misra, Preetham M. Lobo
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Patent number: 11031951Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.Type: GrantFiled: January 14, 2020Date of Patent: June 8, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Slegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
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Patent number: 10985778Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.Type: GrantFiled: January 14, 2020Date of Patent: April 20, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Siegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
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Patent number: 10944423Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.Type: GrantFiled: March 14, 2019Date of Patent: March 9, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Siegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
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Publication number: 20200321976Abstract: Compressing data includes hashing a first token length of an incoming data steam into a hash table, where the first token length includes a plurality of bytes. A second token length of the incoming data stream may be hashed into the hash table. The second token may be larger than the first token length and includes the plurality of bytes. The method may further include automatically comparing which token length enabled more efficient data compression, and automatically adjusting at least one of the first and second token lengths based on the comparison.Type: ApplicationFiled: April 2, 2019Publication date: October 8, 2020Inventors: Bulent ABALI, Ashutosh MISRA, Girish G. KURUP, Deepankar BHATTACHARJEE, Matthias KLEIN
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Publication number: 20200301604Abstract: Various embodiments are provided for managing multiport banked memory arrays in a computing system by a processor. One or more conflicts may be eliminated in a multiport banked memory array upon receiving one or more write operations, read operations, or a combination thereof according to a selected priority and access protocol.Type: ApplicationFiled: March 19, 2019Publication date: September 24, 2020Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bulent ABALI, Ashutosh Misra, Hubertus FRANKE, Matthias KLEIN, Deepankar Bhattacharjee, Girish Kurup
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Publication number: 20200295780Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Inventors: Timothy Slegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
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Publication number: 20200295781Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.Type: ApplicationFiled: January 14, 2020Publication date: September 17, 2020Inventors: Timothy Slegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
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Publication number: 20200293377Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.Type: ApplicationFiled: January 14, 2020Publication date: September 17, 2020Inventors: Timothy Slegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
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Publication number: 20200272565Abstract: A system architecture is provided and includes an on-chip coherency unit, a processing unit, an accelerator and dedicated wiring. The processing unit is communicative with the on-chip coherency unit via a first interface. The accelerator is communicative with the on-chip coherency unit via a second interface. The accelerator is configured to be receptive of a request to execute lossless data compression or decompression from the processing unit and to responsively execute the lossless data compression or decompression faster than the processing unit. The processing unit and the accelerator are directly communicative by way of the dedicated wiring.Type: ApplicationFiled: February 27, 2019Publication date: August 27, 2020Inventors: Matthias Klein, Ashutosh Misra, Girish Gopala Kurup
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Patent number: 10754781Abstract: Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in each of a plurality of performance modes. The method further includes choosing a performance mode based on the monitoring. Thereafter, using the performance mode for a predetermined amount of time. Each of the plurality of performance modes is a branch prediction mode.Type: GrantFiled: February 27, 2017Date of Patent: August 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Ashutosh Misra, Brian R. Prasky
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Patent number: 10756758Abstract: Various embodiments are provided for length-limited Huffman encoding in a data compression accelerator in a computing environment by a processor. Symbol counts of a plurality of symbols in compressed data may be normalized and manipulated according to a maximum code length limiting operation such that those of the plurality of symbols having a least frequent symbol count have a symbol count equal to a maximum code length of a Huffman tree.Type: GrantFiled: August 30, 2019Date of Patent: August 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bulent Abali, Ashutosh Misra, Matthias Klein
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Patent number: 10715174Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for reducing a latch count required for symbol sorting when generating a dynamic Huffman table. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. The accelerator further includes a Huffman encoder communicatively coupled to the LZ77 compressor. The Huffman encoder includes a bit translator. The accelerator further includes an output buffer communicatively coupled to the Huffman encoder.Type: GrantFiled: January 24, 2020Date of Patent: July 14, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bulent Abali, Ashutosh Misra, Suneel Pusarla