Patents by Inventor Ashutosh Misra
Ashutosh Misra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10693493Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for reducing a latch count required for symbol sorting when generating a dynamic Huffman table. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. The accelerator further includes a Huffman encoder communicatively coupled to the LZ77 compressor. The Huffman encoder includes a bit translator. The accelerator further includes an output buffer communicatively coupled to the Huffman encoder.Type: GrantFiled: February 14, 2019Date of Patent: June 23, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bulent Abali, Ashutosh Misra, Suneel Pusarla
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Patent number: 10673460Abstract: An aspect includes a system architecture that includes a processing unit, an accelerator, a main source buffer, a main target buffer, and a memory block. The main source buffer stores a first part of a source symbol received from an external source. The main target buffer stores an output symbol received from the accelerator. The memory block includes an overflow source buffer that stores the first part of the source symbol received from the main source buffer. The accelerator fetches the first part of the source symbol stored in the overflow source buffer and a second part of the source symbol stored in the main source buffer, and converts the first and second parts of the source symbol together into the output symbol. The second part of the source symbol includes a part of the source symbol not included in the first part of the source symbol.Type: GrantFiled: February 27, 2019Date of Patent: June 2, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Girish Gopala Kurup, Matthias Klein, Anthony Thomas Sofia, Jonathan D. Bradbury, Ashutosh Misra, Christian Jacobi, Deepankar Bhattacharjee
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Patent number: 10585626Abstract: A system and method to manage a non-universal encoder and a universal encoder for compression of data include receiving the data. The data includes symbols. The method also includes subdividing the data into a first set of data blocks and a second set of data blocks and generating a non-universal encoder using the first set of data blocks. The non-universal encoder includes first codes. Each of the first codes corresponds to one of the symbols in the first set of data blocks only and at least one of the first codes includes fewer bits than the symbol corresponding to the at least one of the first codes. The method further includes compressing the second set of data blocks using at least the non-universal encoder.Type: GrantFiled: December 7, 2017Date of Patent: March 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan Bradbury, Matthias Klein, Ashutosh Misra, Anthony Sofia
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Patent number: 10409609Abstract: A system, method and computer program product for maintaining an age and validity of entries in a structure associated with a processor is disclosed. An age tracking matrix is created for the structure. Each row of the age tracking matrix corresponds to an entry of the structure and each column of the age tracking matrix corresponds to an entry of the structure. When initiating an entry: a row corresponding to the entry is determined and a field in the determined row that is on a diagonal of the matrix is marked. For each other field in the determined row, the values that are in a diagonal field that is in a same column of the field are copied into the field. A relative age of the entries is determined by counting a number of marked fields in a column of the age tracking matrix.Type: GrantFiled: December 14, 2015Date of Patent: September 10, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Publication number: 20190179572Abstract: A system and method to manage a non-universal encoder and a universal encoder for compression of data include receiving the data. The data includes symbols. The method also includes subdividing the data into a first set of data blocks and a second set of data blocks and generating a non-universal encoder using the first set of data blocks. The non-universal encoder includes first codes. Each of the first codes corresponds to one of the symbols in the first set of data blocks only and at least one of the first codes includes fewer bits than the symbol corresponding to the at least one of the first codes. The method further includes compressing the second set of data blocks using at least the non-universal encoder.Type: ApplicationFiled: December 7, 2017Publication date: June 13, 2019Inventors: Jonathan Bradbury, Matthias Klein, Ashutosh Misra, Anthony Sofia
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Patent number: 10097600Abstract: A method for analyzing streaming data includes providing a streaming accumulator comprising an addition module and two multiplexers, receiving one or more data streams, continuously calculating a set of basic statistical elements, receiving a request to calculate a set of statistical descriptors, calculating the set of statistical descriptors, and providing the set of statistical descriptors. An apparatus for analyzing streaming data includes a first multiplexer configured to receive a first summation, a second summation, and a current data item, and forward the first summation on cycles 1 and 3, forward the second summation on cycle 4, and forward the current data item on cycle 2, a second multiplexer configured to receiver the second summation, a third summation, and a previous data item, and forward the previous data item on cycles 1 and 3, forward the second summation on cycle 4, and forward the third summation on cycle 2.Type: GrantFiled: July 21, 2016Date of Patent: October 9, 2018Assignee: International Business Machines CorporationInventors: Suchismita Banerjee, Girish G. Kurup, Ashutosh Misra, Niranjan Vaish
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Publication number: 20180246811Abstract: Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in each of a plurality of performance modes. The method further includes choosing a performance mode based on the monitoring. Thereafter, using the performance mode for a predetermined amount of time. Each of the plurality of performance modes is a branch prediction mode.Type: ApplicationFiled: February 27, 2017Publication date: August 30, 2018Inventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Ashutosh Misra, Brian R. Prasky
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Patent number: 10033778Abstract: A method for analyzing streaming data includes providing a streaming accumulator comprising an addition module and two multiplexers, receiving one or more data streams, continuously calculating a set of basic statistical elements, receiving a request to calculate a set of statistical descriptors, calculating the set of statistical descriptors, and providing the set of statistical descriptors. An apparatus for analyzing streaming data includes a first multiplexer configured to receive a first summation, a second summation, and a current data item, and forward the first summation on cycles 1 and 3, forward the second summation on cycle 4, and forward the current data item on cycle 2, a second multiplexer configured to receiver the second summation, a third summation, and a previous data item, and forward the previous data item on cycles 1 and 3, forward the second summation on cycle 4, and forward the third summation on cycle 2.Type: GrantFiled: September 29, 2015Date of Patent: July 24, 2018Assignee: International Business Machines CorporationInventors: Suchismita Banerjee, Girish G. Kurup, Ashutosh Misra, Niranjan Vaish
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Patent number: 9934873Abstract: A method includes configuring an integrated circuit comprising one or more registers to provide a free running clock in the integrated circuit, simulating N clock cycles in the circuit to provide performance results for one or more registers in the circuit, wherein N is a selected number of staging levels, selecting one of the one or more registers, comparing the performance results for the selected register to performance results for each of the remaining registers to provide one or more equivalent delay candidate registers, and verifying each of the one or more equivalent delay candidate registers to provide one or more confirmed equivalent delay registers. A corresponding computer program product and computer system are also disclosed.Type: GrantFiled: July 28, 2017Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Raj Kumar Gajavelly, Ashutosh Misra, Pradeep Kumar Nalla, Rahul M. Rao
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Publication number: 20170365362Abstract: A method includes configuring an integrated circuit comprising one or more registers to provide a free running clock in the integrated circuit, simulating N clock cycles in the circuit to provide performance results for one or more registers in the circuit, wherein N is a selected number of staging levels, selecting one of the one or more registers, comparing the performance results for the selected register to performance results for each of the remaining registers to provide one or more equivalent delay candidate registers, and verifying each of the one or more equivalent delay candidate registers to provide one or more confirmed equivalent delay registers. A corresponding computer program product and computer system are also disclosed.Type: ApplicationFiled: July 28, 2017Publication date: December 21, 2017Inventors: Raj Kumar Gajavelly, Ashutosh Misra, Pradeep Kumar Nalla, Rahul M. Rao
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Patent number: 9715564Abstract: A method for performing redundancy identification in an integrated circuit design. An optimized gate in a logic circuit is identified. A first netlist with a representation of the logic circuit is generated. An error is induced on the optimized gate. A second netlist is generated from a copy of the first netlist incorporating changes based on the error. Fan-out boundaries of the logic circuit are propagated for the first and second netlists. A redundancy report representing optimization steps performed to obtain the original logic circuit is analyzed to identify which steps are adequate to cause unobservability of the optimized gate. This is done by representing the optimization steps as constraints over the first and second netlists. Responsive to the error becoming undetectable under the constraints derived from the redundancy report, a minimal set of reductions is identified from the first netlist as the reason for unobservability of the optimized gate.Type: GrantFiled: October 28, 2015Date of Patent: July 25, 2017Assignee: International Business Machines CorporationInventors: Jason R. Baumgartner, Raj K. Gajavelly, Ashutosh Misra, Pradeep K. Nalla
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Patent number: 9697001Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.Type: GrantFiled: October 6, 2016Date of Patent: July 4, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Patent number: 9690587Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.Type: GrantFiled: April 8, 2014Date of Patent: June 27, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Publication number: 20170168824Abstract: A system, method and computer program product for maintaining an age and validity of entries in a structure associated with a processor is disclosed. An age tracking matrix is created for the structure. Each row of the age tracking matrix corresponds to an entry of the structure and each column of the age tracking matrix corresponds to an entry of the structure. When initiating an entry: a row corresponding to the entry is determined and a field in the determined row that is on a diagonal of the matrix is marked. For each other field in the determined row, the values that are in a diagonal field that is in a same column of the field are copied into the field. A relative age of the entries is determined by counting a number of marked fields in a column of the age tracking matrix.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Publication number: 20170124240Abstract: A method for performing redundancy identification in an integrated circuit design. An optimized gate in a logic circuit is identified. A first netlist with a representation of the logic circuit is generated. An error is induced on the optimized gate. A second netlist is generated from a copy of the first netlist incorporating changes based on the error. Fan-out boundaries of the logic circuit are propagated for the first and second netlists. A redundancy report representing optimization steps performed to obtain the original logic circuit is analyzed to identify which steps are adequate to cause unobservability of the optimized gate. This is done by representing the optimization steps as constraints over the first and second netlists. Responsive to the error becoming undetectable under the constraints derived from the redundancy report, a minimal set of reductions is identified from the first netlist as the reason for unobservability of the optimized gate.Type: ApplicationFiled: October 28, 2015Publication date: May 4, 2017Inventors: Jason R. Baumgartner, Raj K. Gajavelly, Ashutosh Misra, Pradeep K. Nalla
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Publication number: 20170093655Abstract: A method for analyzing streaming data includes providing a streaming accumulator comprising an addition module and two multiplexers, receiving one or more data streams, continuously calculating a set of basic statistical elements, receiving a request to calculate a set of statistical descriptors, calculating the set of statistical descriptors, and providing the set of statistical descriptors. An apparatus for analyzing streaming data includes a first multiplexer configured to receive a first summation, a second summation, and a current data item, and forward the first summation on cycles 1 and 3, forward the second summation on cycle 4, and forward the current data item on cycle 2, a second multiplexer configured to receiver the second summation, a third summation, and a previous data item, and forward the previous data item on cycles 1 and 3, forward the second summation on cycle 4, and forward the third summation on cycle 2.Type: ApplicationFiled: September 29, 2015Publication date: March 30, 2017Inventors: Suchismita Banerjee, Girish G. Kurup, Ashutosh Misra, Niranjan Vaish
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Publication number: 20170093656Abstract: A method for analyzing streaming data includes providing a streaming accumulator comprising an addition module and two multiplexers, receiving one or more data streams, continuously calculating a set of basic statistical elements, receiving a request to calculate a set of statistical descriptors, calculating the set of statistical descriptors, and providing the set of statistical descriptors. An apparatus for analyzing streaming data includes a first multiplexer configured to receive a first summation, a second summation, and a current data item, and forward the first summation on cycles 1 and 3, forward the second summation on cycle 4, and forward the current data item on cycle 2, a second multiplexer configured to receiver the second summation, a third summation, and a previous data item, and forward the previous data item on cycles 1 and 3, forward the second summation on cycle 4, and forward the third summation on cycle 2.Type: ApplicationFiled: July 21, 2016Publication date: March 30, 2017Inventors: Suchismita Banerjee, Girish G. Kurup, Ashutosh Misra, Niranjan Vaish
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Publication number: 20170017493Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.Type: ApplicationFiled: October 6, 2016Publication date: January 19, 2017Inventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Patent number: 9513909Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.Type: GrantFiled: March 18, 2016Date of Patent: December 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Publication number: 20160188339Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.Type: ApplicationFiled: March 18, 2016Publication date: June 30, 2016Inventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito