Abstract: A method, an apparatus, and a computer program product for optimising a bus in a Processor Local Bus (PLB) system are disclosed. A master engine performs a transfer transaction of N bytes of data on the bus of the PLB system. A type of read or write data transfer to be performed by the master engine is determined to optimize operation of the bus in response to a transfer request received asynchronously from a device coupled to the bus. This involves a request type determination function. Data is asynchronously transferred using a FIFO between the device and the bus dependent upon the determined type of transfer.

Abstract: An additional bit is used in a binary register for detecting register contents in timing and counting applications. A predetermined timing or counting event occurs when the additional bit changes logical states. In one implementation, an additional bit is provided in the most significant bit (MSB) position in a binary register, and is initially set to a logical zero state. When the values in the binary register decrement to zero, the additional (MSB) bit changes logic states to a logical one state, when the zero value in the binary register is decremented in the next clock cycle. A determination is consequently made that the binary register has reached zero.

Abstract: A dual master apparatus for mastering a Processor Local Bus (PLB), which is a high-performance, on-chip bus used in many System on Chip (SOC) applications, supporting up to 16 masters. The apparatus includes a first circuit for generating an address phase for read data coupled to the PLB, and a second circuit for generating an address phase for write data coupled to the PLB. The second address phase generating circuit is adapted to carry out a write operation when the write data bus is idle and the read data bus is busy, and vice versa. The first and second address phase generating circuits can simultaneously process read and write requests. The apparatus also may include circuits for handling read and write data coupled to the first and second address generating circuits, respectively. Further, the apparatus may include circuits for requesting read and write data coupled to the read- and write-data handling circuits, respectively.

Abstract: Scheduling a sequence of tasks quickly using a task list containing a sequence of entries, with each entry indicating whether a task is enabled or disabled for execution. A scheduler block examines the sequence of entries without wasting time in examining entries between those (entries) related to a prior scheduled task and a task to be scheduled next. By not wasting time examining the entries related to the disabled entries, the next task in the sequence of tasks may be scheduled for execution quickly.

Abstract: An additional bit is used in a binary register for detecting register contents in timing and counting applications. A predetermined timing or counting event occurs when the additional bit changes logical states. In one implementation, an additional bit is provided in the most significant bit (MSB) position in a binary register, and is initially set to a logical zero state. When the values in the binary register decrement to zero, the additional (MSB) bit changes logic states to a logical one state, when the zero value in the binary register is decremented in the next clock cycle. A determination is consequently made that the binary register has reached zero.

Abstract: A method and system select delay values from a VHDL standard delay file that correspond to an instance of a logic gate in a logic model. Then the system collects all the delay values of the selected instance and builds super generics for the rise-time and the fall-time of the selected instance. Then, the system repeats this process for every delay value in the standard delay file (310) that correspond to every instance of every logic gate in the logic model. The system then outputs a reduced size standard delay file (314) containing the super generics for every instance of every logic gate in the logic model.

Abstract: A method and system update a VHDL technology library (306) to incorporate correlated delay values by reading the VHDL technology library (306), inserting a tpd_super_rise_time generic declaration and a tpd_super_fall_time generic declaration for every VHDL gate model in the VHDL technology library (306), initializing other generic variables in every VHDL gate model in the VHDL technology library to an equation representing a correlation policy; and outputting an updated VHDL technology library. Then, the method and system bind correlated delay constants in a 3-dimensional variable data array structure to a VHDL technology library (306) using a VHDL package embedded with the correlation delay data.

Abstract: A method and system unbind a rise/fall tuple of a VHDL generic variable and create rise time and fall time generics of each generic variable that are independent of each other. Then, according to a predetermined correlation policy, the method and system collect delay values in a VHDL standard delay file, sort the delay values, remove duplicate delay values, group the delay values into correlation sets, and output an analysis file. The correlation policy may include collecting all generic variables in a VHDL standard delay file, selecting each generic variable, and performing reductions on the set of delay values associated with each selected generic variable.

Abstract: Provided are slurry compositions suitable for use in a chemical-mechanical planarization process and methods for making same. The compositions include: (a) abrasive particles dispersed in a suspension medium; (b) a peroxygen compound; and (c) a stabilizing agent. The stabilizing agent includes a phosphoric acid, a salt of a phosphoric acid or combinations thereof. The invention has particular applicability to the semiconductor manufacturing industry.

Abstract: Provided are methods and systems for controlling the concentration of a component in a composition, and semiconductor processing methods and systems. One exemplary method of controlling the concentration of a component in a composition involves: providing a composition which has a liquid portion, wherein the liquid portion contains a component to be monitored; performing an absorption spectroscopy measurement on a sample of the composition; and controlling the concentration of the component in the composition based on the absorption spectroscopy measurement using a feedback control loop. The invention allows for controlling the concentration of a component in a composition, for example, a corrosion inhibitor in a chemical planarization (CMP) chemical, as well as in pre- and post-CMP storage/treatment chemicals, and can provide real time, accurate process control in a simple and robust manner.

Abstract: Provided are methods for making a slurry composition, suitable for use in a chemical-mechanical planarization process. Also provided are compositions made by such methods. The methods comprise combining: (a) abrasive particles; (b) a suspension medium; (c) a peroxygen compound; (d) an etching agent; and (e) an alkyl ammonium hydroxide. The methods and compositions of the present invention are particularly applicable to the semiconductor manufacturing industry.

Abstract: An embodiment of the instant invention is a method of fabricating an electrical device having a structure overlying a semiconductor substrate which is planarized using chemical mechanical planarization, the method comprising the steps of: forming a layer of material over the semiconductor wafer; polishing the layer of material by subjecting it to a polishing pad and a slurry which includes peroxygen; and wherein the slurry additionally includes a stabilizing agent which retards the decomposition of the peroxygen in the slurry. Preferably, the stabilizing agent is comprised of: pyrophosphoric acids, polyphosphonic acids, polyphosphoric acids, Ethylenediamine Tetraacetic acid, a salt of the pyrophosphoric acids, a salt of the polyphosphonic acids, a salt of the polyphosphoric acids, a salt of the Ethylenediamine Tetraacetic acid and any combination thereof. In addition, the stabilizing agent may be comprised of: sodium pyrophosphate decahydrate, sodium pyrophosphate decahydrate, and/or 8-hydroxyquinoline.

Abstract: Methods of removing discoloration from a metal surface of an electronic device are presented the methods comprising the steps of exposing a metallic surface of an electronic device to a first composition comprising an organic reagent, the metallic surface having discoloration thereon, under conditions sufficient to form a first intermediate metallic surface substantially devoid of non-ionic residues; a second step of contacting the first intermediate metallic surface with a second composition comprising an acid under conditions sufficient to form a second intermediate metallic surface substantially devoid of non-ionic residues, oxides, hydroxides and the like; and rinsing the second intermediate metallic surface with deionized water.

Abstract: A method of determining a concentration of a component of a slurry includes the step of measuring change in refractive index associated with changes in concentration of the component of interest in the slurry.

Abstract: Provided is a novel method of cleaning a chemical vapor deposition processing chamber having deposits on an inner surface thereof is provided. The process involves forming a plasma from one or more gases comprising a fluorine-containing but otherwise halogen-free non-global-warming compound, and contacting active species generated in the plasma with the inner surface of the chamber, with the proviso that the non-global-warming compound is not trifluoroacetic anhydride. Also provided is a method of etching a layer on a silicon wafer. The method involves the steps of: (a) introducing a silicon wafer into a processing chamber, the silicon wafer comprising a layer to be etched; and (b) forming a plasma from one or more gases comprising a fluorine-containing but otherwise halogen-free non-global-warming compound. Active species generated in the plasma are contacted with the silicon wafer, thereby etching the layer, with the proviso that the non-global-warming compound is not trifluoroacetic anhydride.

Abstract: Traditionally, hydrofluoric acid (HF) or buffered bydrofluoric acid (NH.sub.4 F) is mixed with water to form a etching solution for cleaning silicon dioxide from semiconductor wafer surfaces. An etching solution formed by mixing ammonium hydrogen bifluoride ((NH.sub.4)HF.sub.2) with water provides a benign alternative for cleaning silicon dioxide.

Abstract: This invention is for an improved slurry for shallow trench isolation processing in chemical mechanical polishing of semiconductor devices. The oxide/nitride selectivity is enhanced by increasing the pH of the slurry, increasing the solids content of the slurry and/or by adding a fluoride salt to the slurry. With these modifications, selectivity of greater than 10:1 can be attained.