Patents by Inventor Atsunori Terasaki

Atsunori Terasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7422981
    Abstract: A method for manufacturing a semiconductor device is provided, in which the lengths of a wiring trench and a via hole in a depth direction are easily controlled. A component having a first insulating film is prepared on a substrate, and a layer is disposed on the above-described first insulating film. A mold having a pattern is imprinted on the above-described layer so as to form a second insulating film having a wiring trench and a first via, the pattern corresponding to the wiring trench and the first via. Thereafter, the above-described first insulating film is etched by using the above-described second insulating film as a mask so as to form a second via, which is connected to the first via, in the first insulating film.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: September 9, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Atsunori Terasaki, Junichi Seki, Ichiro Tanaka
  • Publication number: 20080211133
    Abstract: A mold for imprinting a pattern onto a resin material applied onto a substrate is constituted by a mold substrate formed of a material transparent to light in at least a part of a wavelength range of light used for alignment, an alignment structure area having an alignment structure comprising a recess portion, a pattern forming area having a pattern, and a coating layer is formed of a material having an optical characteristic different from that of the mold substrate. The coating layer is on a side wall of the recess portion.
    Type: Application
    Filed: February 19, 2008
    Publication date: September 4, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Atsunori Terasaki, Junichi Seki
  • Publication number: 20080047932
    Abstract: A process for producing a structure containing silicon oxide includes a step of forming a first layer of organic spin-on glass on a substrate and a step of forming a second layer of inorganic spin-on glass on the first layer. Thereafter, the first layer is etched by using a pattern formed on the second layer as a mask and then the first layer and the second layer are calcined to prepare the structure containing silicon oxide.
    Type: Application
    Filed: August 23, 2007
    Publication date: February 28, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Atsunori Terasaki, Junichi Seki, Toshiki Ito
  • Publication number: 20070187875
    Abstract: A mold capable of a highly accurate alignment with a member to be processed in such a state that a photocurable resin material is disposed between the mold and the member to be processed, and is constituted by a substrate 2010 formed of a first material and an alignment mark 2102 formed of a second material different from the first material. The first material and the second material have transmissivities to light in a part of an ultraviolet wavelength range. The second material has a refractive index of not less than 1.7.
    Type: Application
    Filed: August 31, 2006
    Publication date: August 16, 2007
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Atsunori TERASAKI, Junichi SEKI, Nobuhito SUEHIRA, Hideki INA, Shingo OKUSHIMA
  • Publication number: 20070128850
    Abstract: A method for manufacturing a semiconductor device is provided, in which the lengths of a wiring trench and a via hole in a depth direction are easily controlled. A component having a first insulating film is prepared on a substrate, and a layer is disposed on the above-described first insulating film. A mold having a pattern is imprinted on the above-described layer so as to form a second insulating film having a wiring trench and a first via, the pattern corresponding to the wiring trench and the first via. Thereafter, the above-described first insulating film is etched by using the above-described second insulating film as a mask so as to form a second via, which is connected to the first via, in the first insulating film.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 7, 2007
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Atsunori Terasaki, Junichi Seki, Ichiro Tanaka
  • Publication number: 20070090574
    Abstract: In order to provide a mold and an imprint apparatus which permit adjustment of a depth of an imprint pattern after the imprint pattern is formed, the mold is constituted by a mold substrate including a first material and a surface layer, constituting a projection of the mold and including a second material, for forming a pattern on the photocurable resin material. The first material is more etchable than the second material. The first material and the second material have optical transmittances capable of curing the photocurable resin material with respect to at least a part of wavelength range of ultraviolet light.
    Type: Application
    Filed: August 31, 2006
    Publication date: April 26, 2007
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Atsunori Terasaki, Junichi Seki, Nobuhito Suehira, Hideki Ina
  • Publication number: 20060279004
    Abstract: A pattern forming method for forming a pattern includes: preparing a mold 104 provided with a first surface including a pattern area 1000, a second surface located opposite from the first surface, and an alignment mark 2070 provided at a position at which the alignment mark 2070 is away from the second surface and is close to the first surface; contacting the pattern area 1000 of the mold 104 with the coating material disposed on a substrate 5000; obtaining information about positions of the mold 104 and the substrate 5000 by using the alignment mark 2070 and a mark 5300 provided to the substrate 5000 in a state in which the coating material is disposed on the substrate 5000 at a portion where the alignment mark 2070 and the substrate 5000 are opposite to each other; and effecting alignment of the substrate 5000 with the mold 104 with high accuracy on the basis of the information.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 14, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Nobuhito Suehira, Junichi Seki, Masao Majima, Atsunori Terasaki, Hideki Ina
  • Patent number: 7109494
    Abstract: A deflector which makes multilayered wiring possible and prevents contamination during the manufacture includes an electrode substrate (400) having a plurality of through holes, and an electrode pair made up of first and second electrodes which oppose the side walls of each through hole in order to control the locus of a charged particle beam passing through the through hole, and a wiring substrate (500) having connection wiring pads connected to the electrode pairs of the electrode substrate to individually apply voltages to the electrode pairs. This deflector is formed by bonding the electrode substrate and wiring substrate via the connection wiring pads of the wiring substrate.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: September 19, 2006
    Assignees: Canon Kabushiki Kaisha, Hitachi High-Technologies Corporation
    Inventors: Haruhito Ono, Masatake Akaike, Kenji Tamamori, Futoshi Hirose, Yasushi Koyama, Atsunori Terasaki, Ken-ichi Nagae, Yoshinori Nakayama
  • Publication number: 20040169147
    Abstract: A deflector which makes multilayered wiring possible and prevents contamination during the manufacture includes an electrode substrate (400) having a plurality of through holes, and an electrode pair made up of first and second electrodes which oppose the side walls of each through hole in order to control the locus of a charged particle beam passing through the through hole, and a wiring substrate (500) having connection wiring pads connected to the electrode pairs of the electrode substrate to individually apply voltages to the electrode pairs. This deflector is formed by bonding the electrode substrate and wiring substrate via the connection wiring pads of the wiring substrate.
    Type: Application
    Filed: February 27, 2004
    Publication date: September 2, 2004
    Applicants: Canon Kabushiki Kaisha, Hitachi High-Technologies Corporation
    Inventors: Haruhito Ono, Masatake Akaike, Kenji Tamamori, Futoshi Hirose, Yasushi Koyama, Atsunori Terasaki, Ken-ichi Nagae, Yoshinori Nakayama